W3H32M72E-XSBX Datasheet, PDF (13/30 Pages) White Electronic Designs Corporation – 32M x 72 DDR2 SDRAM 208 PBGA Multi-Chip Package

White Electronic Designs
W3H32M72E-XSBX
PRELIMINARY*
EXTENDED MODE REGISTER (EMR)
The extended mode register controls functions beyond
those controlled by the mode register; these additional
functions are DLL enable/disable, output drive strength,
on die termination (ODT) (RTT), posted AL, off-chip driver
impedance calibration (OCD), DQS# enable/disable,
RDQS/RDQS# enable/disable, and output disable/enable.
These functions are controlled via the bits shown in
Figure 7. The EMR is programmed via the LOAD MODE
(LM) command and will retain the stored information
until it is programmed again or the device loses power.
Reprogramming the EMR will not alter the contents of the
memory array, provided it is performed correctly.
The EMR must be loaded when all banks are idle and
no bursts are in progress, and the controller must wait
the specified time ^tMRD before initiating any subsequent
operation. Violating either of these requirements could
result in unspecified operation.
FIGURE 7 – EXTENDED MODE REGISTER DEFINITION
BA1 BA0 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 Address Bus
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MRS 0² out RDQS DQS# OCD Program Rtt Posted CAS# Rtt ODS DLL
Extended Mode
Register (Ex)
E12 Outputs
0 Enabled
1 Disabled
E11 RDQS Enable
0
No
1
Yes
E6 E2 Rtt (nominal)
0 0 Rtt Disabled
0 1 75Ω
1 0 150Ω
1 1 50Ω
E0
DLL Enable
0 Enable (Normal)
1 Disable (Test/Debug)
E1 ^{Output Drive Strength}
0 Full Strength (18 Ω target)
1 Reduced Strength (40 Ω target)
E10 DQS# Enable
0
Enable
1 Disable
E9 E8 E7 OCD Operation
0 0 0 OCD Not Supported ¹
0 0 1 Reserved
0 1 0 Reserved
1 0 0 Reserved
1 1 1 OCD default state ¹
E5 E4 E3 Poste d CAS# Add itive Laten cy (AL)
000
0
001
1
010
2
011
3
100
4
101
Reserved
110
Reserved
111
Reserved
E15 E14
Mo de Register Set
00
Mode Register Set (MR S)
0 1 Extended Mode Register (EMR S)
1 0 Extended Mode Register (EMR S2)
1 1 Extended Mode Register (EMR S3)
Note: 1. During initialization, all three bits must be set to "1" for OCD default state,
then must be set to "0" before initialization is finished, as detailed in the
initialization procedure.
2.. E13 (A13) is not used on this device.
White Electronic Designs Corp. reserves the right to change products or specifications without notice.
February 2006
Rev. 2
13
White Electronic Designs Corporation • [phone] • www.wedc.com