W3H32M72E-XSBX Datasheet, PDF (10/30 Pages) White Electronic Designs Corporation – 32M x 72 DDR2 SDRAM 208 PBGA Multi-Chip Package

White Electronic Designs
W3H32M72E-XSBX
PRELIMINARY*
MODE REGISTER (MR)
The mode register is used to define the specific mode of
operation of the DDR2 SDRAM. This definition includes
the selection of a burst length, burst type, CL, operating
mode, DLL RESET, write recovery, and power-down mode,
as shown in Figure 5. Contents of the mode register can be
altered by re-executing the LOAD MODE (LM) command.
If the user chooses to modify only a subset of the MR
variables, all variables (M0–M14) must be programmed
when the command is issued.
The mode register is programmed via the LM command
(bits BA1–BA0 = 0, 0) and other bits (M12–M0) will retain
the stored information until it is programmed again or
the device loses power (except for bit M8, which is self-
clearing). Reprogramming the mode register will not alter
the contents of the memory array, provided it is performed
correctly.
The LM command can only be issued (or reissued) when all
banks are in the precharged state (idle state) and no bursts
are in progress. The controller must wait the specified
time ^tMRD before initiating any subsequent operations
such as an ACTIVE command. Violating either of these
requirements will result in unspecified operation.
BURST LENGTH
Burst length is defined by bits M0–M3, as shown in Figure
5. Read and write accesses to the DDR2 SDRAM are
burst-oriented, with the burst length being programmable
to either four or eight. The burst length dete rmines
the maximum number of column locations that can be
accessed for a given READ or WRITE command.
When a READ or WRITE command is issued, a block of
columns equal to the burst length is effectively selected.
All accesses for that burst take place within this block,
meaning that the burst will wrap within the block if a
boundary is reached. The block is uniquely selected by
A2–Ai when BL = 4 and by A3–Ai when BL = 8 (where
Ai is the most significant column address bit for a given
configuration). The remaining (least significant) address
bit(s) is (are) used to select the starting location within the
block. The programmed burst length applies to both READ
and WRITE bursts.
FIGURE 5 – MODE REGISTER (MR) DEFINITION
BA1 BA0 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 Address Bus
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Mode Register (Mx)
MR 0¹ PD WR DLL TM CAS# Latency BT Burst Length
M12 PD mode
0 Fast Exit
(Normal)
1 Slow Exit
(Low Power)
M7 Mo de
0 Normal
1 Test
M8 DLL Reset
0 No
1 Yes
M2 M1 M0 Burst Length
0 0 0 Reserved
0 0 1 Reserved
0 10
4
0 11
8
1 0 0 Reserved
1 0 1 Reserved
M11 M10 M9 WRITE RECOVERY
0 00
Reserved
1 10
1 11
Reserved
Reserved
0 01
2
0 10
3
0 11
4
1 00
5
M3
Burst Type
0
Sequential
1
Interleaved
1 01
1 10
1 11
6
Reserved
Reserved
M6 M5 M4
000
001
CAS Latency (CL)
Reserved
Reserved
M15 M14 Mo de Register Definition
00
Mode Register (MR)
0 1 Extended Mode Register (EMR)
1 0 Extended Mode Register (EMR2)
1 1 Extended Mode Register (EMR3)
010
011
100
101
110
111
Reserved
3
4
5
6
Reserved
Note: 1. Not used on this part
BURST TYPE
Accesses within a given burst may be programmed to be
either sequential or interleaved. The burst type is selected
via bit M3, as shown in Figure 5. The ordering of accesses
within a burst is determined by the burst length, the burst
type, and the starting column address, as shown in Table
2. DDR2 SDRAM supports 4-bit burst mode and 8-bit burst
mode only. For 8-bit burst mode, full interleave address
ordering is supported; however, sequential address
ordering is nibble-based.
White Electronic Designs Corp. reserves the right to change products or specifications without notice.
February 2006
Rev. 2
10
White Electronic Designs Corporation • [phone] • www.wedc.com