W3H32M72E-XSBX Datasheet, PDF (19/30 Pages) White Electronic Designs Corporation – 32M x 72 DDR2 SDRAM 208 PBGA Multi-Chip Package

White Electronic Designs
W3H32M72E-XSBX
PRELIMINARY*
READ COMMAND
The READ command is used to initiate a burst read access
to an active row. The value on the BA1–BA0 inputs selects
the bank, and the address provided on inputs A0–i (where
i = A9) selects the starting column location. The value on
input A10 determines whether or not auto precharge is
used. If auto precharge is selected, the row being accessed
will be precharged at the end of the READ burst; if auto
precharge is not selected, the row will remain open for
subsequent accesses.
READ OPERATION
READ bursts are initiated with a READ command. The
starting column and bank addresses are provided with the
READ command and auto precharge is either enabled or
disabled for that burst access. If auto precharge is enabled,
the row being accessed is automatically precharged at the
completion of the burst. If auto precharge is disabled, the
row will be left open after the completion of the burst.
During READ bursts, the valid data-out element from the
starting column address will be available READ latency
(RL) clocks later. RL is defined as the sum of AL and CL;
RL = AL + CL. The value for AL and CL are programmable
via the MR and EMR commands, respectively. Each
subsequent data-out element will be valid nominally at
the next positive or negative clock edge (i.e., at the next
crossing of CK and CK#).
DQS/DQS# is driven by the DDR2 SDRAM along with
output data. The initial LOW state on DQS and HIGH state
on DQS# is known as the read preamble (^tRPRE). The
LOW state on DQS and HIGH state on DQS# coincident
with the last data-out element is known as the read
postamble (^tRPST).
Upon completion of a burst, assuming no other commands
have been initiated, the DQ will go High-Z.
Data from any READ burst may be concatenated with
data from a subsequent READ command to provide a
continuous flow of data. The first data element from the
new burst follows the last element of a completed burst.
The new READ command should be issued x cycles after
the first READ command, where x equals BL / 2 cycles.
FIGURE 11 – READ COMMAND
CK#
CK
CKE
CS#
RAS#
CAS#
WE#
ADDRESS
AUTO PRECHARGE
BANK ADDRESS
Col
ENABLE
A10
DISABLE
Bank
DON’T CARE
White Electronic Designs Corp. reserves the right to change products or specifications without notice.
February 2006
Rev. 2
19
White Electronic Designs Corporation • [phone] • www.wedc.com