W3H32M72E-XSBX Datasheet, PDF (27/30 Pages) White Electronic Designs Corporation – 32M x 72 DDR2 SDRAM 208 PBGA Multi-Chip Package

White Electronic Designs
W3H32M72E-XSBX
PRELIMINARY*
AC TIMING PARAMETERS (continued)
-55°C ≤ TA < +125°C; VCCQ = + 1.8V ± 0.1V, VCC = +1.8V ± 0.1V
Parameter
Address and control input pulse width for each input
Address and control input setup time
Address and control input hold time
CAS# to CAS# command delay
ACTIVE to ACTIVE (same bank) command
ACTIVE bank a to ACTIVE bank b command
ACTIVE to READ or WRITE delay
Four Bank Activate period
ACTIVE to PRECHARGE command
Internal READ to precharge command delay
Write recovery time
Auto precharge write recovery + precharge time
Internal WRITE to READ command delay
PRECHARGE command period
PRECHARGE ALL command period
LOAD MODE command cycle time
CKE low to CK, CK# uncertainty
REFRESH to Active or Refresh to Refresh command interval
Average periodic refresh interval
Exit self refresh to non-READ command
Exit self refresh to READ
Exit self refresh timing reference
ODT tum-on delay
ODT turn-on
ODT turn-off delay
ODT tum-off
ODT tum-on (power-down mode)
ODT turn-off (power-down mode)
ODT to power-down entry latency
ODT power-down exit latency
Exit active power-down to READ command, MR[bit12=0]
Exit active power-down to READ command, MR[bit12=1]
Exit precharge power-down to any non-READ command
CKE minimum high/low time
Symbol
tIPW
tISa
tISb
tIHa
tIHb
tCCD
tRC
tRRD
tRCD
tFAW
tRAS
tRTP
tWR
tDAL
tWTR
tRP
tRPA
tMRD
tDELAY
tRFC
tREFI
tXSNR
tXSRD
tlSXR
tAOND
tACN
tAOFD
tAOF
tAONPD
tAOFPD
tANPD
tAXPD
tXARD
tXARDS
tXP
tCKE
533Mbs CL4
Min
Max
400Mbs CL3
Unit
Min
Max
0.6
0.6
tCK
500
600
ps
250
350
ps
500
600
ps
375
475
ps
2
2
ps
55
55
ns
10
10
ns
15
15
ns
50
50
ns
40
70,000
40
70,000
ns
7.5
7.5
ns
15
15
ns
tWR + tRP
tWR + tRP
ns
7.5
10
ns
15
15
ns
tRP + tCK
tRP + tCK
ns
2
2
tCK
tIS +tIH + tCK
tIS +tIH + tCK
ns
105
70,000
105
70,000
ns
7.8
7.8
ns
tRPC(MIN) + 10
tRFC(MIN) + 10
ns
200
200
tCK
tIS
tIS
ps
2
2
2
2
tCK
tAC(MIN) tAC(MAX) + 1000 tAC(MIN) tAC(MAX) + 1000 ps
2.5
2.5
2.5
2.5
tCK
tAC(MIN)
tAC(MAX) +
tAC(MIN)
tAC(MAX) +
ps
600
600
tAC(MIN) +
2 x tCK +
tAC(MIN) +
2 x tCK +
ps
2000 tAC(MAX) + 1000 2000 tAC(MAX) + 1000
tAC(MIN) +
2 x tCK +
tAC(MIN) +
2 x tCK +
ps
2000 tAC(MAX) + 1000 2000 tAC(MAX) + 1000
3
3
tCK
8
8
tCK
2
2
tCK
6-AL
6-AL
tCK
2
2
tCK
3
3
tCK
White Electronic Designs Corp. reserves the right to change products or specifications without notice.
February 2006
Rev. 2
27
White Electronic Designs Corporation • [phone] • www.wedc.com