W3H32M72E-XSBX Datasheet, PDF (17/30 Pages) White Electronic Designs Corporation – 32M x 72 DDR2 SDRAM 208 PBGA Multi-Chip Package

White Electronic Designs
W3H32M72E-XSBX
PRELIMINARY*
TABLE 3 – TRUTH TABLE - DDR2 COMMANDS
Notes appear on page 9
Function
CKE
Previous Current
CS#
RAS# CAS# WE#
BA1
BA0
A12
A11
A10 A9-A0 Notes
Cycle
Cycle
LOAD MODE
H
H
L
L
L
L
BA
OP Code
2
REFRESH
H
H
L
L
L
H
X
X
X
X
SELF-REFRESH Entry
H
L
L
L
L
H
X
X
X
X
H
X
X
X
SELF-REFRESH Exit
L
H
X
X
X
X
7
L
H
H
H
Single bank precharge
H
H
L
L
H
L
X
X
L
X
2
All banks PRECHARGE
H
H
L
L
H
L
X
X
H
X
Bank activate
H
H
L
L
H
L
BA
Row Address
WRITE
H
H
L
L
H
L
BA
Column
Address
L
Column
Address
2, 3
WRITE with auto precharge
H
H
L
H
L
L
BA
Column
Address
H
Column
Address
2, 3
READ
H
H
L
H
L
H
BA
Column
Address
L
Column
Address
2, 3
READ with auto precharge
H
H
L
H
L
H
BA
Column
Address
H
Column
Address
2, 3
NO OPERATION
H
X
L
H
H
H
X
X
X
X
Device DESELECT
H
X
H
X
X
X
X
X
X
X
POWER-DOWN entry
H
H
X
X
X
L
X
X
X
X
4
L
H
H
H
H
X
X
X
POWER-DOWN exit
L
H
X
X
X
X
4
L
H
H
H
Note: 1. All DDR2 SDRAM commands are defined by states of CS#, RAS#, CAS#, WE#, and CKE at the rising edge of the clock.
2. Bank addresses (BA) BA0–BA12 determine which bank is to be operated upon. BA during a LM command selects which mode register is programmed.
3. 3. Burst reads or writes at BL = 4 cannot be terminated or interrupted.
4. The power-down mode does not perform any REFRESH operations. The duration of power-down is therefore limited by the refresh requirements outlined in the AC
parametric section.
5. The state of ODT does not affect the states described in this table. The ODT function is not available during self refresh. See “On-Die Termination (ODT)” for details.
6. “X” means “H or L” (but a defined logic level).
7. Self refresh exit is asynchronous.
White Electronic Designs Corp. reserves the right to change products or specifications without notice.
February 2006
Rev. 2
17
White Electronic Designs Corporation • [phone] • www.wedc.com