W3H32M72E-XSBX Datasheet, PDF (5/30 Pages) White Electronic Designs Corporation – 32M x 72 DDR2 SDRAM 208 PBGA Multi-Chip Package

White Electronic Designs
W3H32M72E-XSBX
PRELIMINARY*
A0-A12
DQ0-71
UDQS, UDQS#
LDQS, LDQS#
VCC
VCCQ
VREF
VSS
NC
DNU
Input
I/O
I/O
I/O
Supply
Supply
Supply
Supply
-
-
TABLE – 1 BALL DESCRIPTIONS (continued)
Address inputs: Provide the row address for ACTIVE commands, and the column address and auto precharge bit
(A10) for READ/WRITE commands, to select one location out of the memory array in the respective bank. A10
sampled during a PRECHARGE command determines whether the PRECHARGE applies to one bank (A10 LOW,
bank selected by BA1–BA0) or all banks (A10 HIGH) The address inputs also provide the op-code during a LOAD
MODE command.
Data input/output: Bidirectional data bus
Data strobe for upper byte: Output with read data, input with write data for source synchronous operation. Edge-
aligned with read data, center-aligned with write data. UDQS# is only used when differential data strobe mode is
enabled via the LOAD MODE command.
Data strobe for lower byte: Output with read data, input with write data for source synchronous operation. Edge-
aligned with read data, center-aligned with write data. UDQS# is only used when differential data strobe mode is
enabled via the LOAD MODE command.
Power Supply: 1.8V ±0.1V
DQ Power supply: 1.8V ±0.1V. Isolated on the device for improved noise immunity
SSTL_18 reference voltage.
Ground
No connect: These balls should be left unconnected.
Future use; Row address bits A14 and A15 are reserved for 8Gb and 16Gb densities. BA2 is reserved for 4Gb
device.
White Electronic Designs Corp. reserves the right to change products or specifications without notice.
February 2006
Rev. 2
5
White Electronic Designs Corporation • [phone] • www.wedc.com