DS90UR910Q_14 Datasheet, PDF (9/31 Pages) Texas Instruments – 10 - 75 MHz 24-bit Color FPD-Link II to CSI-2 Converter

DS90UR910Q
www.ti.com
SNLS414C – JUNE 2012 – REVISED MAY 2013
AC SWITCHING CHARACTERISTICS (continued)
Over recommended operating supply and temperature ranges unless otherwise specified.
Symbol
σV/σtSR
Parameter
Slew rate
Conditions
Cload = 0pF^(3)(4)(5)
Cload = 5pF^(3)(4)(5)
Cload = 20pF^(3)(4)(5)
Cload = 70pF^(3)(4)(5)
Min
Typ
Max
500
300
250
150
Cload = 0 to 70pF (Falling Edge
Only) ^{(3) (4) (5) (6)}
30
Cload = 0 to 70pF (Rising Edge
Only) ^{(3) (4) (5)}
30
Cload = 0 to 70pF (Rising Edge
Only) ^{(3) (4) (7) (8)}
30 – 0.075
*
(V_O,INST –
700)
C_LOAD
Load capacitance
See ⁽⁴⁾
0
70
Data-Clock Timing Specifications (DATA0±, DATA1±, CLK±) Section 9.2.1 of MIPI D-PHY Specification
UI_INST
Instantaneous Unit Interval
Figure 4
PCLK = 10 – 75 MHz⁽⁹⁾
1/
(PCLK*12)
t_SKEW(TX)
Data to Clock Skew
Figure 4
Skew between Clock and data from
ideal center⁽²⁾
0.5-0.15
0.5
0.5+0.15
CSI-2 Timing Specifications (DATA0±, DATA1±, CLK±)⁽²⁾ (Figure 5, Figure 6) Section 5.9 of MIPI D-PHY Specification
t_CLK-POST
t_CLK-PRE
HS exit
Time HS clock shall be driver prior
to any associated Data Lane
beginning the transition from LP to
HS mode
60 +
52*UI_INST
8
t_CLK-PREPARE
t_CLK-SETTLE
Clock Lane HS Entry
Time interval during which the HS
receiver shall ignore any Clock Lane
HS transitions
38
95
95
300
t_CLK-TERM-EN Time-out at Clock Lane Display
Module to enable HS Termination
38
t_CLK-TRAIL
Time that the transmitter drives the
HS-0 state after the last payload
30
clock bit of a HS transmission burst
t_CLK-PREPARE
+ t_CLK-ZERO
t_D-TERM-EN ⁽¹⁰⁾
t_LPX
t_HS-PREPARE
TCLK-PREPARE + time that the
transmitter drives the HS-0 state
prior to starting the Clock
Time for the Data Lane receiver to
enable the HS line termination
Transmitted length of LP state
Data Lane HS Entry
t_HS-PREPARE +
t_HS-ZERO
tHS-PREPARE + time that the
transmitter drives the HS-0 state
prior to transmitting the Sync
sequence
300
35 ns +
4*UI_INST
50
40 +
4*UI_INST
145 +
10*UI_INST
85 +
6*UI_INST
t_HS-SETTLE
Interval HS receiver shall ignore any
Data Lane HS transitions
85 +
6*UI_INST
145 +
10*UI_INST
Units
mV/ns
mV/ns
mV/ns
mV/ns
mV/ns
mV/ns
mV/ns
pF
ns
UI_INST
ns
UI_INST
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
(5) Measured as average across any 50 mV segment of the output signal transition.
(6) When the output voltage is between 400 mV and 930 mV.
(7) Where VO,INST is the instantaneous output voltage, VDP or VDN, in millivolts.
(8) When the output voltage is between 700 mV and 930 mV.
(9) UI_INST is equal to 1/(12*PCLK), where PCLK is the fundamental frequency for data transmission.
(10) This parameter value can be lower then TLPX due to differences in rise vs. fall signal slopes and trip levels and mismatches between
Dp and Dn LP transmitters. Any LP exclusive-OR pulse observed during HS EoT (transition from HS level to LP-11) is glitch behavior as
described in D-PHY ver 1.00.00.
Copyright © 2012–2013, Texas Instruments Incorporated
Submit Documentation Feedback
9
Product Folder Links: DS90UR910Q