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DS90UR910Q_14 Datasheet, PDF (15/31 Pages) Texas Instruments – 10 - 75 MHz 24-bit Color FPD-Link II to CSI-2 Converter
DS90UR910Q
www.ti.com
SNLS414C – JUNE 2012 – REVISED MAY 2013
FUNCTIONAL DESCRIPTION
The DS90UR910Q recovers RBG data and sync signals from a FPD-Link II AC coupled serial bit stream, and
converts the recovered data into packetized CSI-2 data format. The CSI-2 output serial interface greatly reduces
the interconnect and signal count to a graphic processing unit and eases system designs for video streams from
multiple automotive driver assist cameras.
The DS90UR910Q is based on the DS90UR906Q de-serializer core. Please refer to the DS90UR906Q
datasheet for the functionality and performance of the FPD-Link II interface can be found in the DS90UR906Q
datasheet.
The DS90UR910Q conforms to the MIPI CSI-2 and DPHY standards for protocol and electrical specifications.
Compliant with standards:
• Conforms with MIPI Alliance Specification for D-PHY, version 1.00.00, dated May 14, 2009
• Compatible with MIPI Alliance Standard for Camera Serial Interface 2 (CSI-2) Version 1.01, dated Nov 9,
2010
The DS90UR910Q receives 24-bit (or 18-bit) RGB data and 3 low speed control signals (VS, HS, DE) over a
serial FPD-Link II transmitted through a single twisted pair. It supports a pixel clock of 10 MHz to 75 MHz,
corresponding to the serial line rate of 280 Mb/s to 2100 Mb/s. The serial bit stream contains the scrambled 24-
bit data, an embedded clock, encoded control signals and DC balance information which enhances signal quality
and supports AC coupling.
The DS90UR910Q is compatible with FPD-Link II serializers such as DS90UR905Q, DS90UR241Q,
DS90C241Q, DS90UR907Q, DS99R421Q and DS90UH/UB/925Q FPD-Link III serializers in backward
compatibility mode. The serial bit stream is illustrated in Figure 9. In each pixel clock cycle, a 28-bit frame is
transmitted over the FPD-Link. The frame contains C1 and C0 representing the embedded clock information. C1
is always high and C0 is always low. Payload bits b[23:0] contain the scrambled 24-bit RGB data. DCB is the DC
balance bit and is used to minimize the DC offset on the signal line. DCA is used to validate the data integrity in
the embedded data stream and contain the encoded control signals VS, HS and DE (DS90UR905Q,
DS90UR907Q and DS90UH/UB/925Q in backward compatible mode).
C
1
b
0
b
1
b
2
b
3
b
4
b
5
b
6
b
7
b
8
b
9
b
1
0
b
1
1
D
C
A
D
C
B
b
1
2
b
1
3
b
1
4
b
1
5
b
1
6
b
1
7
b
1
8
b
1
9
b
2
0
b
2
1
b
2
2
b
2
3
C
0
Figure 9. FPD-Link II Serial Stream
The DS90UR910Q supports compatibility to FPD-Link II serializers and FPD-Link III serializers in backward
compatible mode as defined in Table 1.
CON
FIG1
0
0
1
1
CON
FIG0
0
1
0
1
Table 1. DS90UR910Q Configuration Modes
Mode
FPD-Link II Compatibility
Normal Mode, Control Signal Filter disabled
Normal Mode, Control Signal Filter enabled
Backwards Compatible GEN2
Backwards Compatible GEN1
DS90UR905Q 24-bit
DS90UR907Q 24-bit
DS90UH/UB/925Q 24-bit
DS90UR905Q 24-bit
DS90UR907Q 24-bit
DS90UH/UB/925Q 24-bit
DS90UR241Q 18-bit
DS99R421Q 18-bit
DS90C241Q 18-bit
CSI-2 Data
Format
RGB888
RGB888
RGB888
RGB888
INPUT RECEIVE EQUALIZATION
The input equalizer of the DS90UR910Q is designed to compensate the attenuation distortion results from cable
of different length or wire gauge. The equalizer gain setting is controlled by the control pins EQ[3:1] or through
register programming. Users can optimize the equalizer’s gain setting along with the de-emphasis level of the
DS90UR905Q/907Q to achieve the optimum jitter performance.
Copyright © 2012–2013, Texas Instruments Incorporated
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