DS90UR910Q_14 Datasheet, PDF (25/31 Pages) Texas Instruments – 10 - 75 MHz 24-bit Color FPD-Link II to CSI-2 Converter

DS90UR910Q
www.ti.com
SNLS414C – JUNE 2012 – REVISED MAY 2013
ULTRA LOW POWER STATE
DS90UR910Q D-PHY Lanes will enter ULPS mode upon software standby mode through CCI generated by
Application Processor. When ULPS is entered, all lanes including the clock and data lanes are put in ULPS
according to the MIPI D-PHY protocol. D-PHY can reduce power consumption by entering ULPS mode.
Ultra-Low Power State Entry Command is sent after an Escape mode Entry command through CCI, and then
Lane shall enter the Ultra-Low Power State (ULPS). When ULPS is entered, all lanes including the clock and
data lanes are put in ULPS according to the MIPI DPHY protocol. Typically an ULPS entry command is used but
other sequences can be used also. Ultra-Low Power State is exited by means of a Mark-1 state with a length
TWAKEUP followed by a Stop state. Reference: [1] D-PHY Specification, Section 5.6.3, Line 895
Frame
End
Stop Escape
(LP11) Mode
Ultra-Low-Power-State Entry Command 00011110
Clock Lane
Dp/Dn
ULPS
(LP00)
Mark-1
(LP10)
Stop
(LP11)
Data Lane
Dp/Dn
tLPX
tWAKEUP tINIT
Figure 14. Ultra-Low Power State
DISPLAY TIMING REQUIREMENTS
Table 7 shows the supported display resolutions for the DS90UR910Q. The display timings assume an estimated
overall blanking rate of 1.2. The DS90UR910Q will automatically detect the incoming data rate by from the frame
rate (by measuring VS). This timing is then mapped into a look up table. The lookup table is used for any pixel
rate from PCLK of 10 MHz to 65 MHz. The limitation that it assumes the frame rate is 60fps and 30fps. An
override option will be available to set each of the parameter individually for a data rate that is not listed in the
table. Option is programmed through CCI. Operation of frequencies above 65 MHz require additional I2C/CCI
programming of CSI_TIMING registers.
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