DS90UR910Q_14 Datasheet, PDF (27/31 Pages) Texas Instruments – 10 - 75 MHz 24-bit Color FPD-Link II to CSI-2 Converter

DS90UR910Q
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APPLICATIONS INFORMATION
SNLS414C – JUNE 2012 – REVISED MAY 2013
TYPICAL APPLICATION CONNECTION
Figure 15 shows a typical application of the DS90UR910Q in Pin control mode for a 24-bit Color Display
Application. The LVDS signals require 100 nF AC coupling capacitors to the line. The line driver includes internal
termination. Bypass capacitors are placed near the power supply pins. At a minimum, four 0.1 µF capacitors and
a 4.7 µF capacitor should be used for local device bypassing. System GPO (General Purpose Output) signals
control the PDB and BISTEN pins. The interface to the host is with 1.8 V LVCMOS levels, thus the VDDIO pin is
connected also to the 1.8V rail. The Optional I2C/CCI is connected to the Host bus in this example, thus the SCL
and SDA pins are using pull-up resistors R to VDDIO. A delay cap is placed on the PDB signal to delay the
enabling of the device until power is stable.
1.8V
FB1
1.8V
3.3V
FB1, FB2:
1 NŸ @100 MHz
DC R < 1Ÿ
2.2 µF
ceramic
FB2
0.1 µF
0.1 µF
VDDCSI VDDL
0.1 µF
4.7 µF
ceramic
0.1 µF ^{2.2 µF}
ceramic
VDDA
0.1 µF ^VDDP
VDDIO
Data1+
0.1 µF
Data1-
RIN+
Data0+
From FPD-Link II
Serializer
100Ÿ 673
4.7 µF
ceramic
0.1 µF
CMF
RIN-
Data0-
CLK+
CLK-
VDDIO
DS90UR910Q
RR
GPU
100: (1%)
Strap
High or Low
CMLOUT+
SCL
SDA
CMLOUT-
CONFIG[1:0]
EQ[3:1]
ID[1:0]
RES
GND
DAP
LOCK
BISTEN
PASS
PDB
Optional
Control pins
10 k: ^VDDIO
10 µF
Figure 15. DS90UR910Q Typical Connection Diagram — Pin Control
POWER UP REQUIREMENTS AND PDB PIN
The VDD (V_DDn and V_DDIO) supply ramp should be faster than 1.5 ms with a monotonic rise. If slower then 1.5 ms
then a capacitor on the PDB pin is needed to ensure PDB arrives after all the VDD have settled to the
recommended operating voltage. When PDB pin is pulled to V_DDIO, it is recommended to use a 10 kΩ pull-up and
a >10 uF cap to GND to delay the PDB input signal.
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