DS90UR910Q_14 Datasheet, PDF (17/31 Pages) Texas Instruments – 10 - 75 MHz 24-bit Color FPD-Link II to CSI-2 Converter

www.ti.com
FS
Line Blanking
Frame Blanking
Line Data
DS90UR910Q
SNLS414C – JUNE 2012 – REVISED MAY 2013
FE
(1 to N) t_LPX ^{Frame Blanking}
FS
Line Blanking
Line Data
FE
Frame Blanking
Figure 10. General Frame Format
HIGH SPEED CLOCK AND DATA
The high speed clock and data outputs are source synchronous interface. The half rate clock at CLK± is derived
from the pixel clock sourced by the clock/data recovery circuit of the DS90UR910Q. The clock frequency is 6
times the Pixel clock frequency. The 24-bit recovered RGB data is serialized and output at the 2 high speed data
lanes DATA0± and DATA1± in according to the CSI-2 protocol. The data rate of each lane is 12 times the Pixel
clock. As an example, at a pixel clock of 75 MHz, the CLK± runs at 450 MHz, and the data lanes run at 900
Mb/s.
The half-rate clock maintains a quadrature phase relationship to the data signals and allows receiver to sample
data at the rising and falling edges of the clock. Figure 4 shows the timing relationship of the clock and data
lines. The DS90UR910Q supports continuous high speed clock.
High speed data are sent out at DATA0± and DATA1± in bursts. In between data bursts, the data lanes return to
Low Power States in according to protocol defined in D-PHY standard. The rising edge of the differential clock
(CLK+ – CLK-) is sent during the first payload bit of a transmission burst in the data lanes.
The DS90UR910Q recovers the data bits R[7:0], G[7:0], B[7:0], VS, HS and DE from the serial FPD-Link II bit
stream at RIN±. During the vertical blanking period (VS goes low), it sends the short Frame End packet, followed
by a short Frame Start packet. User can program the time between Frame End to Frame Start packets from 0 to
(2¹⁶-1) in units of 8*pclk_period/3.
NON-CONTINUOUS/CONTINUOUS CLOCK
DS90UR910Q D-PHY supports Continuous clock mode and Non-Continuous clock mode. Default mode is Non-
Continuous Clock mode, where the Clock Lane enters in LP mode between the transmissions of data packets.
Non-continuous clock mode will only be non-continuous during the vertical blanking period for lower PCLK rates.
For higher PCLK rates, the clock will be non-continuous between line and frame packets. Operating modes are
configurable through CCI.
Copyright © 2012–2013, Texas Instruments Incorporated
Product Folder Links: DS90UR910Q
Submit Documentation Feedback
17