DS90UR910Q_14 Datasheet, PDF (12/31 Pages) Texas Instruments – 10 - 75 MHz 24-bit Color FPD-Link II to CSI-2 Converter

DS90UR910Q
SNLS414C – JUNE 2012 – REVISED MAY 2013
AC TIMING DIAGRAMS AND TEST CIRCUITS
Ideal Data Bit
Beginning
Sampling
Window
Ideal Data
Bit End
RxIN_TOL
Left
V_TH
0V
RxIN_TOL
Right
V_TL
Ideal Center Position (t_BIT/2)
t_BIT (1 UI)
t_IJT = RxIN_TOL (Left + Right)
Sampling Window = 1 UI - t_IJT
Figure 2. Receiver Input Jitter Tolerance
www.ti.com
PDB
(3.3V I/O)
2.2V
RIN
(Diff.)
LOCK TRI-STATE
t_DDLT
0.8V
TRI-STATE
DATA0+/-
DATA1+/-
CLK+/-
OFF
IN LOCK TIME
ACTIVE
OFF
Figure 3. Deserializer PLL Lock Time
DATA1+
DATA1-
DATA0+
DATA0-
CLK+
0.5UI +
tskew
CLK-
1 UI
Figure 4. Clock and Data Timing in HS Transmission
12
Submit Documentation Feedback
Copyright © 2012–2013, Texas Instruments Incorporated
Product Folder Links: DS90UR910Q