DS90UR910Q_14 Datasheet, PDF (18/31 Pages) Texas Instruments – 10 - 75 MHz 24-bit Color FPD-Link II to CSI-2 Converter

DS90UR910Q
SNLS414C – JUNE 2012 – REVISED MAY 2013
www.ti.com
Clock lane enters LP11 during horizontal blanking if the horizontal blanking period is longer than the overhead
time to start/stop the clock lane. There is auto-detection of the length of the horizontal blank period. The
threshold is 70 PCLK cycles. Register bit available to disable off the non-continuous clock mode
DATA FRAME RGB MAPPING
Table 3 shows the pixel data R[7:0], G[7:0 and B[7:0] defined in DS90UR905Q/907Q and DS90UH/UB/925Q
pinout, which are recovered by the DS90UR910Q and output in RGB888 format at the CSI-2 interface.
Table 3. CSI-2 RGB888 Data Format with FPD-Link II Serializer (24-bit mode)
FPD-Link II (24-bit)
pin name
R[0]
R[1]
R[2]
R[3]
R[4]
R[5]
R[6]
R[7]
G[0]
G[1]
G[2]
G[3]
G[4]
G[5]
G[6]
G[7]
B[0]
B[1]
B[2]
B[3]
B[4]
B[5]
B[6]
B[7]
HS
VS
DE
RGB888 Data bits
R[0]
R[1]
R[2]
R[3]
R[4]
R[5]
R[6]
R[7]
G[0]
G[1]
G[2]
G[3]
G[4]
G[5]
G[6]
G[7]
B[0]
B[1]
B[2]
B[3]
B[4]
B[5]
B[6]
B[7]
DE
LANE1
DATA0±
LPS
SoT
ID
WC_byte1 B1
R1
G2
...
Rn-1
Gn
CRC_byte0 EoT
LPS
LANE2 _LPS
SoT
WC_byte0 ECC
G1
B2
R2
...
Bn
Rn ^CRC_byte1 EoT
LPS
DATA1±
Figure 11. DATA0± and DATA1± packet format in according to CSI-2 protocol for RGB888
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