DS90UR910Q_14 Datasheet, PDF (23/31 Pages) Texas Instruments – 10 - 75 MHz 24-bit Color FPD-Link II to CSI-2 Converter

DS90UR910Q
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ADD
(hex)
0x11
Register Name
CSI config
0x12 CSI_FRM_GAP_0
0x13 CSI_FRM_GAP_1
0x14 CSI_TIMING0
0x15 CSI_TIMING1
0x16 CSI_TIMING2
0x17 CSI_TIMING3
0x18 CSI_TIMING4
SNLS414C – JUNE 2012 – REVISED MAY 2013
Table 6. Serial Bus Control Registers (continued)
Bit(s) R/W Default Field
Description
7
R/W
6
R/W
5:2 R/W
1
R/W
0
R/W
7:0 R/W
7:0 R/W
7:5
4:0 R/W
7:3 R/W
2:0 R/W
7:4 R/W
3:0 R/W
7
R/W
6:4 R/W
3:0 R/W
7:3 R/W
2:0 R/W
0
CCI_INV_VS
0: VS is active low pulse
1: VS is active high pulse
0
CCI_CONT_CLOCK
0: CSI-2 non-continuous clock
1: CSI-2 continuous clock
0
Reserved
Reserved
0
CCI_EXTERNAL_TIMING
0: Use computed DPHY timing
based on frame length
1: Use manual override values
for DPHY timing
0
CCI_INV_DE
0: DE is active low pulse
1: DE is active high pulse
0
CSI_FRM_GAP_0
Defined the delay between the
start frame and end frame
packet (lower byte)
0
CSI_FRM_GAP_1
Defined the delay between the
start frame and end frame
packet (upper byte)
0
Reserved
Reserved
0
TCLK_PREPARE
Defines the Tclk_prepare
parameter if
CCI_EXTERNAL_TIMING is
set
0
TCLK_ZERO
Defines the Tclk_zero
parameter if
CCI_EXTERNAL_TIMING is
set
0
TCLK_TRAIL
Defines the Tclk_trail
parameter if
CCI_EXTERNAL_TIMING is
set
0
TCLK_POST
Defines the Tclk_post
parameter if
CCI_EXTERNAL_TIMING is
set
0
THS_ZERO
Defines the Ths_zero
parameter if
CCI_EXTERNAL_TIMING is
set
0
Reserved
Reserved
0
THS_TRAIL
Defines the Ths_trail
parameter if
CCI_EXTERNAL_TIMING is
set
0
THS_EXIT
Defines the Ths_exit
parameter if
CCI_EXTERNAL_TIMING is
set
0
THS_PREPARE
Defines the Ths_prepare
parameter if
CCI_EXTERNAL_TIMING is
set
0
TLPX
Defines the Ths_exit
parameter if
CCI_EXTERNAL_TIMING is
set
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