DS90UR910Q_14 Datasheet, PDF (3/31 Pages) Texas Instruments – 10 - 75 MHz 24-bit Color FPD-Link II to CSI-2 Converter

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PIN DIAGRAM
DS90UR910Q
SNLS414C – JUNE 2012 – REVISED MAY 2013
30 29 28 27 26 25 24 23 22 21
VDDA 31
GND 32
RIN+ ³³
RIN- ₃₄
CMF ³⁵
GND ³⁶
CMLOUT+ 37
CMLOUT- 38
VDDA 39
VDDP 40
DS90UR910Q
40-Pin WQFN
(Top View)
DAP = GND
20
VDDCSI
19
DATA1+
18
DATA1-
17
GND
16
DATA0+
15
DATA0-
14
GND
13
CLK+
12
CLK-
11
CONFIG[0]
12 3
4
5
67
8
9 10
Figure 1. Top View
Pin Name
Pin #
FPD-Link II Serial Interface
RIN+
33
RIN-
34
CMF
35
CMLOUT+
37
CMLOUT-
38
MIPI Interface
DATA1+
19
DATA1-
18
DATA0+
16
DATA0-
15
CLK+
13
CLK-
12
(1) 1 = HIGH, 0 = LOW
I/O, Type
PIN DESCRIPTIONS⁽¹⁾
Description
I, CML
I, Analog
O, CML
Inverting and non-inverting differential inputs. The inputs must be AC Coupled with a 100 nF
capacitor.
Common mode filter pin for the differential inputs. CMP is the virtual ground of the differential
input stage. A bypass capacitor is connected from CMP to ground to increase the receiver’s
common mode noise immunity. A 4.7 µF ceramic capacitor is recommended.
Inverting and non-inverting differential outputs. Single 100Ω (1%) termination resistor must
be placed across the CMLOUT± pins. Optional loop-through output to monitor post equalizer
and requires use of the Serial Control Bus to enable.
O, DPHY
O, DPHY
O, DPHY
O, DPHY
O, DPHY
O, DPHY
Inverting and non-inverting data output of DPHY Lane 1
Inverting and non-inverting data output of DPHY Lane 0
Inverting and non-inverting half-rate DPHY clock lane
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