DS90UR910Q_14 Datasheet, PDF (4/31 Pages) Texas Instruments – 10 - 75 MHz 24-bit Color FPD-Link II to CSI-2 Converter

DS90UR910Q
SNLS414C – JUNE 2012 – REVISED MAY 2013
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PIN DESCRIPTIONS⁽¹⁾ (continued)
Pin Name
Pin #
I/O, Type
Description
Control and Configuration
PDB
Power Down Mode Input
30
I, LVCMOS
w/ pull-down
PDB = 1, Device is enabled (normal operation)
PDB = 0, Device is in power-down
When the device is in the power-down, outputs are TRI-STATE, control registers are
RESET.
CONFIG[1:0]
10, 11
I, LVCMOS Operating Mode Select
w/ pull-down CONFIG[1:0] selects compatibility to FPD-Link II serializers. See Table 1.
EQ[3:1]
1, 2, 3
I, LVCMOS
w/ pull-down
Receive equalization control
EQ[3:1] provides 8 combinations of the receive equalization gain settings. See Table 2.
EQ[3:1] optimizes the input equalizer’s ability to reduce inter-symbol interference from the
loss characteristics of different cable lengths.
BISTEN
29
I, LVCMOS
w/ pull-down
BIST Enable Input
BISTEN = 1, BIST is enabled
BISTEN = 0, BIST is disabled
LOCK
LOCK Status Output
24
O, LVCMOS LOCK = 1, PLL acquired lock to the reference clock input; DPHY outputs are active
LOCK = 0, PLL is unlocked
PASS
Normal mode status output pin (BISTEN = 0)
PASS = 1: No fault detected on input display timing
PASS = 0: Indicates an error condition or corruption in display timing. Fault condition occurs
if:
25
O, LVCMOS 1) DE length value mismatch measured once in succession
2) VSync length value mismatch measured twice in succession
BIST mode status output pin (BISTEN = 1)
PASS = 1: No error detected
PASS = 0: Error detected
CCI / I2C Serial Control Bus
SCL
SDA
ID[1:0]
6
I, LVCMOS, Serial Control Bus Clock Input
Open Drain SCL requires an external pull-up resistor to V_DDIO.
5
I/O, LVCMOS Serial Control Bus Data Input / Output
Open Drain SDA requires an external pull-up resistor to V_DDIO.
8, 9
I, LVCMOS Serial Control Bus Device ID Address Select
w/ pull-down See Table 5.
Reserved Pins
GPIO
21
I/O
General Purpose I/O
Note: Pin must be left floating during initial power-up.
RES
28
I, LVCMOS
w/ pull-down
Reserved pin. Must tie Low.
Power and Ground
VDDL
7
Power Power to logic circuitry, 1.8V ±5%
VDDA
39
Power Power to analog circuitry, 1.8V ±5%
VDDP
40
Power Power to PLL, 1.8V ±5%
VDDCSI
20
Power Power to DPHY CSI-2 drivers, 1.8V ±5%
VDDIO
GND
23
4, 14, 17,
22, 27, 32,
36
Power
Ground
Power to LVCMOS I/O circuitry, 1.8V ±5% OR 3.3V ±10% (V_DDIO)
Ground return.
GND
DAP
Ground
DAP is the metal contact at the bottom side, located at the center of the WQFN package. It
should be connected to the GND plane with multiple via to lower the ground impedance and
improve the thermal performance of the package. Connected to the ground plane (GND) with
at least 9 vias.
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
4
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