DRV8303_15 Datasheet, PDF (9/37 Pages) Texas Instruments – Three Phase Gate Driver

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DRV8303
SLOS846B – SEPTEMBER 2013 – REVISED NOVEMBER 2015
6.8 Gate Timing and Protection Switching Characteristics
PARAMETER
TEST CONDITIONS
MIN TYP MAX UNIT
TIMING, OUTPUT PINS
t_pd,If-O
t_pd,Ir-O
t_{d_min}
t_dtp
t_GDr
t_GDF
t_{ON_MIN}
Positive input falling to GH_x falling
Positive input rising to GL_x falling
Minimum dead time after hand shaking⁽¹⁾
Dead Time
Rise time, gate drive output
Fall time, gate drive output
Minimum on pulse
CL=1 nF, 50% to 50%
CL=1 nF, 50% to 50%
With R_DTC set to different values
CL=1 nF, 10% to 90%
CL=1 nF, 90% to 10%
Not including handshake communication.
Hi-Z to on state, output of gate driver
45
ns
45
ns
50 ns
50
500 ns
25
ns
25
ns
50 ns
t_{pd_match}
Propagation delay matching between high
side and low side
5 ns
t_{dt_match}
Deadtime matching
TIMING, PROTECTION AND CONTROL
5 ns
t_{pd,R_GATE-OP}
Start-up time, from EN_GATE active high
to device ready for normal operation
PVDD is up before start up, all charge
pump caps and regulator caps as in
recommended condition
5
10 ms
t_{pd,R_GATE-Quick}
If EN_GATE goes from high to low and
back to high state within quick reset time,
it will only reset all faults and gate driver
without powering down charge pump,
current amp, and related internal voltage
regulators.
Maximum low pulse time
10 us
t_pd,E-L
t_pd,E-FAULT
Delay, error event to all gates low
Delay, error event to FAULT low
200
ns
200
ns
(1) Dead time programming definition: Adjustable delay from GH_x falling edge to GL_X rising edge, and GL_X falling edge to GH_X rising
edge. This is a minimum dead-time insertion. It is not added to the value set by the microcontroller externally.
SCS
t_{HI_SCS}
_
t_{SU_SCS}
t_{HD_SCS}
SCLK
t_CLK
t_CLKH
t_CLKL
SDI
SDO
Z
t_ACC
MSB in
(must be valid)
LSB
t_{SU_SDI} t_{HD_SDI}
MSB out (is valid)
LSB
t_{D_SDO}
t_{HD_SDO}
Figure 1. SPI Slave Mode Timing Definition
Z
t_DIS
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