DRV8303_15 Datasheet, PDF (3/37 Pages) Texas Instruments – Three Phase Gate Driver

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5 Pin Configuration and Functions
DRV8303
SLOS846B – SEPTEMBER 2013 – REVISED NOVEMBER 2015
nOCTW 1
nFAULT 2
DTC 3
nSCS 4
SDI 5
SDO 6
SCLK 7
DC_CAL 8
GVDD 9
CP1 10
CP2 11
EN_GATE 12
INH_A 13
INL_A 14
INH_B 15
INL_B 16
INH_C 17
INL_C 18
DVDD 19
REF 20
SO1 21
SO2 22
AVDD 23
AGND 24
DCA Package
48-Pin TSSOP Pad Down
Top View
48 GND
47 GND
46 GND
45 VDD_SPI
44 BST_A
43 GH_A
42 SH_A
41 GL_A
40 SL_A
39 BST_B
38 GH_B
37 SH_B
36 GL_B
35 SL_B
34 BST_C
33 GH_C
32 SH_C
31 GL_C
30 SL_C
29 SN1
28 SP1
27 SN2
26 SP2
25 PVDD
PIN
NAME
NO.
nOCTW
1
nFAULT
2
DTC
3
nSCS
4
SDI
5
SDO
6
SCLK
7
DC_CAL
8
GVDD
9
CP1
10
CP2
11
EN_GATE
12
INH_A
13
INL_A
14
INH_B
15
INL_B
16
INH_C
17
INL_C
18
Pin Functions
I/O
DESCRIPTION
O
Overcurrent or/and over temperature warning indicator. This output is open drain with external pullup
resistor required. Programmable output mode through SPI registers.
O Fault report indicator. This output is open drain with external pullup resistor required.
I Dead-time adjustment with external resistor to GND
I SPI chip select
I SPI input
O SPI output
I SPI clock signal
I
When DC_CAL is high, device shorts inputs of shunt amplifiers and disconnects loads. DC offset
calibration can be done through external microcontroller.
P Internal gate driver voltage regulator. GVDD cap should connect to GND
P Charge pump pin 1, ceramic cap should be used between CP1 and CP2
P Charge pump pin 2, ceramic cap should be used between CP1 and CP2
I Enable gate driver and current shunt amplifiers.
I PWM Input signal (high side), half-bridge A
I PWM Input signal (low side), half-bridge A
I PWM Input signal (high side), half-bridge B
I PWM Input signal (low side), half-bridge B
I PWM Input signal (high side), half-bridge C
I PWM Input signal (low side), half-bridge C
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