DRV8303_15 Datasheet, PDF (27/37 Pages) Texas Instruments – Three Phase Gate Driver

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10 Layout
DRV8303
SLOS846B – SEPTEMBER 2013 – REVISED NOVEMBER 2015
10.1 Layout Guidelines
Use these layout recommendations when designing a PCB for the DRV8303.
• The DRV8303 makes an electrical connection to GND through the PowerPAD. Always check to ensure that
the PowerPAD has been properly soldered (See PowerPAD™ Thermally Enhanced Package application
report, SLMA002).
• PVDD bypass capacitors should be placed close to their corresponding pins with a low impedance path to
device GND (PowerPAD).
• GVDD bypass capacitor should be placed close its corresponding pin with a low impedance path to device
GND (PowerPAD).
• AVDD and DVDD bypass capacitors should be placed close to their corresponding pins with a low impedance
path to the AGND pin. It is preferable to make this connection on the same layer.
• AGND should be tied to device GND (PowerPAD) through a low impedance trace/copper fill.
• Add stitching vias to reduce the impedance of the GND path from the top to bottom side.
• Try to clear the space around and underneath the DRV8303 to allow for better heat spreading from the
PowerPAD.
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