DRV8303_15 Datasheet, PDF (8/37 Pages) Texas Instruments – Three Phase Gate Driver

DRV8303
SLOS846B – SEPTEMBER 2013 – REVISED NOVEMBER 2015
6.6 Current Shunt Amplifier Characteristics
Over operating free-air temperature range.
PARAMETER
TEST CONDITIONS
G1
Gain option 1
Tc = –40°C to 125°C
G2
Gain option 2
Tc = –40°C to 125°C
G3
Gain Option 3
Tc = –40°C to 125°C
G4
Gain Option 4
Tc = –40°C to 125°C
Tsettling
Settling time to 1%
Tc = 0 to 60°C, G = 10, Vstep = 2 V
Tsettling
Settling time to 1%
Tc = 0 to 60°C, G = 20, Vstep = 2 V
Tsettling
Settling time to 1%
Tc = 0 to 60°C, G = 40, Vstep = 2 V
Tsettling
Settling time to 1%
Tc = 0 to 60°C, G = 80, Vstep = 2 V
Vswing
Output swing linear range
Slew Rate
G = 10
DC_offset
Offset error RTI
G = 10 with input shorted
Drift_offset
Offset drift RTI
Ibias
Input bias current
Vin_com
Common input mode range
Vin_dif
Differential input range
Vo_bias
Output bias
With zero input current, Vref up to
6V
CMRR_OV
Overall CMRR with gain resistor
mismatch
CMRR at DC, gain = 10
6.7 SPI Characteristics (Slave Mode Only)
t_{SPI_READY}
t_CLK
t_CLKH
t_CLKL
t_{SU_SDI}
t_{HD_SDI}
t_{D_SDO}
t_{HD_SDO}
t_{SU_SCS}
t_{HD_SCS}
t_{HI_SCS}
t_ACC
t_DIS
SPI ready after EN_GATE transitions
to HIGH
Minimum SPI clock period
Clock high time
Clock low time
SDI input data setup time
SDI input data hold time
SDO output data delay time, CLK
high to SDO valid
SDO output data hold time
SCS setup time
SCS hold time
SCS minimum high time before SCS
active low
SCS access time, SCS low to SDO
out of high impedance
SCS disable time, SCS high to SDO
high impedance
PVDD > 6 V
See Figure 1
See Figure 1
C_L = 20 pF
See Figure 1
See Figure 1
www.ti.com
MIN
TYP
9.5
10
18
20
38
40
75
80
300
600
1.2
2.4
0.3
10
10
–0.15
–0.3
–0.5%
70
0.5×Vref
85
MAX
10.5
21
42
85
5.7
4
100
0.15
0.3
0.5%
UNIT
V/V
V/V
V/V
V/V
ns
ns
µs
µs
V
V/µs
mV
µV/C
µA
V
V
V
dB
MIN NOM MAX UNIT
5
10
ms
100
ns
40
40
20
ns
30
ns
20
ns
40
50
ns
50
ns
40
ns
10
ns
10
ns
8
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