DRV8303_15 Datasheet, PDF (2/37 Pages) Texas Instruments – Three Phase Gate Driver

DRV8303
SLOS846B – SEPTEMBER 2013 – REVISED NOVEMBER 2015
www.ti.com
Table of Contents
1 Features .................................................................. 1
2 Applications ........................................................... 1
3 Description ............................................................. 1
4 Revision History..................................................... 2
5 Pin Configuration and Functions ......................... 3
6 Specifications......................................................... 5
6.1 Absolute Maximum Ratings ...................................... 5
6.2 ESD Ratings.............................................................. 5
6.3 Recommended Operating Conditions....................... 6
6.4 Thermal Information .................................................. 6
6.5 Electrical Characteristics........................................... 6
6.6 Current Shunt Amplifier Characteristics.................... 8
6.7 SPI Characteristics (Slave Mode Only)..................... 8
6.8 Gate Timing and Protection Switching
Characteristics ........................................................... 9
6.9 Typical Characteristics ............................................ 10
7 Detailed Description ............................................ 11
7.1 Overview ................................................................. 11
7.2 Functional Block Diagram ....................................... 12
7.3 Feature Description................................................. 13
7.4 Device Functional Modes........................................ 17
7.5 Programming........................................................... 19
7.6 Register Maps ......................................................... 20
8 Application and Implementation ........................ 22
8.1 Application Information............................................ 22
8.2 Typical Application ................................................. 23
9 Power Supply Recommendations...................... 26
9.1 Bulk Capacitance .................................................... 26
10 Layout................................................................... 27
10.1 Layout Guidelines ................................................. 27
10.2 Layout Example .................................................... 28
11 Device and Documentation Support ................. 29
11.1 Community Resources.......................................... 29
11.2 Trademarks ........................................................... 29
11.3 Electrostatic Discharge Caution ............................ 29
11.4 Glossary ................................................................ 29
12 Mechanical, Packaging, and Orderable
Information ........................................................... 29
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision A (October 2013) to Revision B
Page
• Added ESD Ratings table, Feature Description section, Device Functional Modes, Application and Implementation
section, Power Supply Recommendations section, Layout section, Device and Documentation Support section, and
Mechanical, Packaging, and Orderable Information section ................................................................................................. 1
• Updated title............................................................................................................................................................................ 1
• V_PVDD absolute max voltage rating reduced from 70 V to 65 V ............................................................................................. 5
• Clarification made on how the OCP status bits report in Overcurrent Protection (OCP) and Reporting ............................ 15
• Update to PVDD undervoltage protection in Undervoltage Protection (UVLO) describing specific transient brownout
issue. .................................................................................................................................................................................... 16
• Update to EN_GATE pin functional description in EN_GATE clarifying proper EN_GATE reset pulse lengths. ................ 17
• Added gate driver power-up sequencing errata .................................................................................................................. 22
2
Submit Documentation Feedback
Product Folder Links: DRV8303
Copyright © 2013–2015, Texas Instruments Incorporated