DRV8303_15 Datasheet, PDF (5/37 Pages) Texas Instruments – Three Phase Gate Driver

www.ti.com
DRV8303
SLOS846B – SEPTEMBER 2013 – REVISED NOVEMBER 2015
6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)⁽¹⁾
V_PVDD
V_PGND
I_{IN_MAX}
I_{SINK_MAX}
V_{OPA_IN}
V_LOGIC
V_GVDD
V_AVDD
V_DVDD
V_{VDD_SPI}
V_SDO
V_REF
I_REF
T_stg
Supply voltage
Relative to PGND
Maximum supply voltage ramp rate
Voltage rising up to PVDD_MAX
Maximum voltage between PGND and GND
Maximum current for all digital and analog inputs (INH_A, INL_A, INH_B, INL_B,
INH_C, INL_C, SCLK, SCS, SDI, EN_GATE, DC_CAL, DTC)
Maximum sinking current for open-drain pins (nFAULT and nOCTW Pins)
Voltage range for SPx and SNx pins
Input voltage range for logic/digital pins (INH_A, INL_A, INH_B, INL_B, INH_C,
INL_C, EN_GATE, SCLK, SDI, SCS, DC_CAL)
Maximum voltage for GVDD Pin
Maximum voltage for AVDD Pin
Maximum voltage for DVDD Pin
Maximum voltage for VDD_SPI Pin
Maximum voltage for SDO Pin
Maximum reference voltage for current amplifier
Maximum current for REF Pin
Storage temperature
MIN
–0.3
–0.3
–1
–0.6
-0.3
100
–55
MAX
65
1
0.3
1
7
0.6
7
13.2
8
3.6
7
V_{DD_SPI}
+0.3
7
150
UNIT
V
V/µs
V
mA
mA
V
V
V
V
V
V
V
V
µA
°C
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
6.2 ESD Ratings
V_(ESD)
Electrostatic discharge
Human body model (HBM), per ANSI/ESDA/JEDEC JS-001, all pins⁽¹⁾
Charged device model (CDM), per JEDEC specification JESD22-C101, all
pins ⁽²⁾
VALUE
±2000
±500
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
UNIT
V
Copyright © 2013–2015, Texas Instruments Incorporated
Product Folder Links: DRV8303
Submit Documentation Feedback
5