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DRV8303_15 Datasheet, PDF (20/37 Pages) Texas Instruments – Three Phase Gate Driver
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DRV8303
SLOS846B – SEPTEMBER 2013 – REVISED NOVEMBER 2015
www.ti.com
Table 6. SPI Output Data Response Word Format
R/W
DATA
Word Bit B15 B14 B13 B12 B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0
Command F0 A3 A2 A1 A0 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
7.6 Register Maps
7.6.1 Read / Write Bit
The MSB bit of the SDI input word (W0) is a read/write bit. When W0 = 0, the input word is a write command.
When W0 = 1, input word is a read command.
7.6.2 Address Bits
REGISTER
TYPE
Status
Register
Control
Register
ADDRESS [A3..A0]
0000
0001
0010
0011
Table 7. Register Address
REGISTER NAME
Status Register 1
Status Register 2
Control Register 1
Control Register 2
DESCRIPTION
Status register for device faults
Status register for device faults and ID
READ AND WRITE ACCESS
R
R
R/W
R/W
7.6.3 SPI Data Bits
7.6.3.1 Status Registers
ADDRESS
0x00
REGISTER
NAME
Status
Register 1
Table 8. Status Register 1 (Address: 0x00) (all default values are zero)
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
FAULT GVDD_UV PVDD_UV
OTSD
OTW
FETHA_OC FETLA_OC FETHB_OC FETLB_OC FETHC_OC FETLC_OC
ADDRESS
0x01
REGISTER
NAME
Status
Register 2
Table 9. Status Register 2 (Address: 0x01) (all default values are zero)
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
GVDD_OV
Device ID
[3]
Device ID
[2]
Device ID
[1]
Device ID
[0]
7.6.3.2 Control Registers
Table 10. Control Register 1 for Gate Driver Control (Address: 0x02)(1)
ADDRES
S
0x02
NAME
DESCRIPTION
Gate drive peak current 1.7 A
Gate drive peak current 0.7 A
GATE_CURRENT
Gate drive peak current 0.25 A
Reserved
GATE_RESET
Normal mode
Reset gate driver latched faults (reverts to 0)
PWM_MODE
6 PWM inputs (see Table 1)
3 PWM inputs (see Table 2)
Current limit
OCP_MODE
OC latch shut down
Report only
OC disabled
OC_ADJ_SET See OC_ADJ_SET table
D10 D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
0 (1)
0 (1)
0
1
1
0
1
1
0 (1)
1
0 (1)
1
0 (1)
0 (1)
0
1
1
0
1
1
X
X
X
X
X
(1) Default value
20
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