DRV8303_15 Datasheet, PDF (15/37 Pages) Texas Instruments – Three Phase Gate Driver

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DRV8303
SLOS846B – SEPTEMBER 2013 – REVISED NOVEMBER 2015
7.3.3 Protection Features
The DRV8303 provides a broad range of protection features and fault condition reporting. The DRV8303 has
undervoltage and over-temperature protection for the IC. It also has overcurrent and undervoltage protection for
the MOSFET power stage. In fault shut down conditions all gate driver outputs will be held low to ensure the
external MOSFETs are in a high impedance state.
7.3.3.1 Power Stage Protection
The DRV8303 provides over-current and undervoltage protection for the MOSFET power stage. During fault shut
down conditions, all gate driver outputs will be kept low to ensure external FETs at high impedance state.
7.3.3.2 Overcurrent Protection (OCP) and Reporting
To protect the power stage from damage due to excessive currents, VDS sensing circuitry is implemented in the
DRV8303. Based on the RDS(on) of the external MOSFETs and the maximum allowed IDS, a voltage threshold
can be determined to trigger the overcurrent protection features when exceeded. The voltage threshold is
programmed through the SPI registers. Overcurrent protection should be used as a protection scheme only; it is
not intended as a precise current regulation scheme. There can be up to a 20% tolerance across channels for
the VDS trip point.
V_DS = I_DS × R_DS(ON)
(2)
The V_DS sense circuit measures the voltage from the drain to the source of the external MOSFET while the
MOSFET is enabled. The high-side sense is between the PVDD and SH_X pins. The low-side sense is between
the SH_X and SL_X pins. Ensuring a differential, low impedance connection to the external MOSFETs for these
lines will help provide accurate V_DS sensing .
There are four different overcurrent modes (OC_MODE) that can be set through the SPI registers. The OC status
bits operate in latched mode. When an overcurrent condition occurs the corresponding OC status bit will latch in
the DRV8303 registers until the fault is reset.
1. Current Limit Mode: In current limit mode the device uses current limiting instead of device shutdown during
an overcurrent event. In this mode the device reports overcurrent events through the nOCTW pin. The
nOCTW pin will be held low for a maximum 64µs period (internal timer) or until the next PWM cycle. If
another overcurrent event is triggered from another MOSFET, during a previous overcurrent event, the
reporting will continue for another 64µs period (internal timer will restart) or until both PWM signals cycle.
The associated status bit will be asserted for the MOSFET in which the overcurrent was detected. There are
two current control settings in current limit mode. These are set by one bit in the SPI registers. The default
mode is cycle by cycle (CBC).
– Cycle-By-Cycle Mode (CBC): In CBC mode, the MOSFET on which overcurrent has been detected on
will shut off until the next PWM cycle.
– Off-Time Control Mode: In Off-Time mode, the MOSFET in which overcurrent has been detected is
disabled for a 64µs period (set by internal timer). If overcurrent is detected in another MOSFET, the timer
will be reset for another 64µs period and both MOSFETs will be disabled for the duration. During this
period, normal operation can be restored for a specific MOSFET with a corresponding PWM cycle.
2. OC Latch Shut Down Mode: When an overcurrent event occurs, both the high-side and low-side MOSFETs
will be disabled in the corresponding half-bridge. The nFAULT pin, nFAULT status bit, and OC status bit for
the MOSFET in which the overcurrent was detected will latch until the fault is reset through the
GATE_RESET bit or a quick EN_GATE reset pulse.
3. Report Only Mode: No protective action will be taken in this mode when an overcurrent event occurs. The
overcurrent event will be reported through the nOCTW pin (64µs pulse) and SPI status register. The external
MCU should take action based on its own control algorithm.
4. OC Disable Mode: The device will ignore and not report all overcurrent detections.
7.3.3.3 Undervoltage Protection (UVLO)
To protect the power output stage during start-up, shutdown, and other possible undervoltage conditions, the
DRV8303 provides undervoltage protection by driving the gate drive outputs (GH_X, GL_X) low whenever PVDD
or GVDD are below their undervoltage thresholds (PVDD_UV/GVDD_UV). This will put the external MOSFETs in
a high impedance state. When the device is in PVDD_UV it will not respond to SPI commands and the SPI
registers will revert to their default settings.
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