DRV8303_15 Datasheet, PDF (17/37 Pages) Texas Instruments – Three Phase Gate Driver

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EVENT
OTSD_GATE
External FET
overload – current
limit mode
External FET
overload – Latch
mode
External FET
overload –
reporting only
mode
DRV8303
SLOS846B – SEPTEMBER 2013 – REVISED NOVEMBER 2015
Table 4. Fault and Warning Reporting and Handling (continued)
ACTION
Gate driver latched shut down.
Weak pulldown of all gate driver
output
to force external FETs HiZ
Shut down the charge pump
LATCH
REPORTING ON REPORTING ON
nFAULT PIN
nOCTW PIN
REPORTING IN SPI
STATUS REGISTER
Y
Y
Y
Y
External FETs current Limiting
(only OC detected FET)
N
N
Y
Y, indicates which phase
has OC
Weak pulldown of gate driver
output and PWM logic “0” of
LS and HS in the same phase.
Y
Y
Y
Y
External FETs HiZ
Reporting only
N
N
Y
Y, indicates which phase
has OC
7.3.4 Start-Up and Shutdown Sequence Control
During power up, all gate drive outputs are held low. Normal operation of gate driver and current shunt amplifiers
can be initiated by toggling EN_GATE from a low state to a high state. If no errors are present, the DRV8303 is
ready to accept PWM inputs. Gate driver always has control of the power FETs even in gate disable mode as
long as PVDD is within functional region.
There is an internal diode from SDO to VDD_SPI, so VDD_SPI is required to be powered to the same power
level as other SPI devices (if there is any SDO signal from other devices) all the time. VDD_SPI supply should
be powered up first before any signal appears at SDO pin and powered down after completing all
communications at SDO pin.
7.4 Device Functional Modes
7.4.1 EN_GATE
EN_GATE low is used to put gate driver, charge pump, current shunt amplifier, and internal regulator blocks into
a low power consumption mode to save energy. SPI communication is not supported during this state. Device
will put the MOSFET output stage to high impedance mode as long as PVDD is still present.
When EN_GATE pin goes to high, it will go through a power-up sequence, and enable gate driver, current
amplifiers, charge pump, internal regulator, and so forth, and reset all latched faults related to gate driver block. It
will also reset status registers in SPI table. All latched faults can be reset when EN_GATE is toggled after an
error event unless the fault is still present.
When EN_GATE goes from high to low, it will shut down gate driver block immediately, so gate output can put
external FETs in high impedance mode. It will then wait for 10us before completely shutting down the rest of the
blocks. A quick fault reset mode can be done by toggling EN_GATE pin for a very short period (less than 10µS).
This will prevent device to shut down other function blocks such as charge pump and internal regulators and
bring a quicker and simple fault recovery. SPI will still function with such a quick EN_GATE reset mode.
The other way to reset all the faults is to use SPI command (RESET_GATE), which will only reset gate driver
block and all the SPI status registers without shutting down other function blocks.
One exception is to reset a GVDD_OV fault. A quick EN_GATE quick fault reset or SPI command reset won’t
work with GVDD_OV fault. A complete EN_GATE with low level holding longer than 10µS is required to reset
GVDD_OV fault. TI highly recommends inspecting the system and board when GVDD_OV occurs.
7.4.2 DTC
Dead time can be programmed through DTC pin. A resistor should be connected from DTC to ground to control
the dead time. Dead time control range is from 50 ns to 500 ns. Short DTC pin to ground will provide minimum
dead time (50 ns). Resistor range is 0 kΩ to 150 kΩ. Dead time is linearly set over this resistor range.
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