DS92LV0411_14 Datasheet, PDF (8/53 Pages) Texas Instruments – 5 - 50 MHz Channel Link II Serializer/Deserializer with LVDS Parallel Interface

DS92LV0411, DS92LV0412
SNLS331B – MAY 2010 – REVISED APRIL 2013
www.ti.com
DS92LV0412 PIN DESCRIPTIONS (continued)
Pin Name
Pin #
I/O, Type Description
Optional BIST Mode
BISTEN
29
I, LVCMOS BIST Mode — Optional
w/ pull-down BISTEN = 1, BIST is enabled
BISTEN = 0, BIST is disabled
PASS
28
O, LVCMOS PASS Output (BIST Mode) — Optional
PASS =1, no errors detected
PASS = 0, errors detected
Leave open if unused. Route to a test point (pad) recommended.
Optional Serial Bus Control
ID[x]
12
I, Analog Serial Control Bus Device ID Address Select — Optional
Resistor to Ground and 10 kΩ pull-up to 1.8V rail. (See Table 11)
SCL
5
I, LVCMOS Serial Control Bus Clock Input - Optional
Open Drain SCL requires an external pull-up resistor to 3.3V.
SDA
4
Power and Ground⁽¹⁾
I/O, LVCMOS Serial Control Bus Data Input / Output - Optional
Open Drain SDA requires an external pull-up resistor 3.3V.
VDDL
6, 31
Power Logic Power, 1.8 V ±5%
VDDA
38, 43
Power Analog Power, 1.8 V ±5%
VDDP
8
Power PLL Power, 1.8 V ±5%
VDDSC
46, 47
Power
SSC Generator Power, 1.8 V ±5%. Power must be connected to these pins regardless if the
SSCG feature is used or not.
VDDTX
13
Power Channel Link LVDS Parallel Output Power, 3.3 V ±10%
VDDIO
25
Power LVCMOS I/O Power and Channel Link I/O Power 1.8 V ±5% OR 3.3 V ±10%
GND
9, 14, 26, 32,
39, 44, 45, 48
Ground Ground
DAP
DAP
Ground
DAP is the large metal contact at the bottom side, located at the center of the WQFN
package. Connect to the ground plane (GND) with at least 9 vias.
(1) 1= HIGH, 0 = LOW. The VDD (V_DDn and V_DDIO) supply ramp should be faster than 1.5 ms with a monotonic rise. If slower then 1.5 ms
then a capacitor on the PDB pin is needed to ensure PDB arrives after all the VDD have settled to the recommended operating voltage.
8
Submit Documentation Feedback
Copyright © 2010–2013, Texas Instruments Incorporated
Product Folder Links: DS92LV0411 DS92LV0412