DS92LV0411_14 Datasheet, PDF (13/53 Pages) Texas Instruments – 5 - 50 MHz Channel Link II Serializer/Deserializer with LVDS Parallel Interface

DS92LV0411, DS92LV0412
www.ti.com
SNLS331B – MAY 2010 – REVISED APRIL 2013
DC Electrical Characteristics (continued)
Over recommended operating supply and temperature ranges unless otherwise specified.^{(1)(2)(3)(4)(5)}
Symbol
Parameter
Conditions
Pin/Freq.
Min
Typ
Max
Uni
ts
I_DD2
I_DDTX2
Supply Current
(Includes load current)
50 MHz Clock
Checker Board
Pattern,
VODSEL = H,
SSCG [2:0] = 111
V_DDn = 1.89
V
V_DDTX = 3.6
V
All V_DD(1:8)
pins
V_DDTX
95
mA
40
mA
I_DDIO2
V_DDIO = 1.89 V_DDIO
V
0.3
mA
I_DDZ
I_DDTXZ
Supply Current Power Down
PDB = 0V,
All other LVCMOS
Inputs = 0V
V_DDIO = 3.6 V
V_DD = 1.89 V All V_DD(1:8)
pins
V_DDTX = 3.6 V_DDTX
V
0.8
mA
0.15
2
mA
0.01
0.1 mA
I_DDIOZ
V_DDIO = 1.89 V_DDIO
V
0.01
0.08 mA
V_DDIO = 3.6V
0.01
0.08 mA
Switching Characteristics
Over recommended operating supply and temperature ranges unless otherwise specified.
Symbol
Parameter
Conditions
DS92LV0411 CHANNEL LINK PARALLEL LVDS INPUT
t_RSP0 Receiver Strobe Position-bit 0
t_RSP1 Receiver Strobe Position-bit 1
t_RSP2
t_RSP3
t_RSP4
Receiver Strobe Position-bit 2
Receiver Strobe Position-bit 3
Receiver Strobe Position-bit 4
RxCLKIN = 50 MHz,
RxIN[3:0]
(See Figure 7)
t_RSP5 Receiver Strobe Position-bit 5
t_RSP6 Receiver Strobe Position-bit 6
DS92LV0412 CHANNEL LINK PARALLEL LVDS OUTPUT
t_LHT
t_THLT
t_DCCJ
Low to High Transition Time
High to Low Transition Time
Cycle-to-Cycle Output Jitter⁽¹⁾
R_L = 100Ω
TxCLKOUT± = 5 MHz
TxCLKOUT± = 50 MHz
t_TTP1
t_TTP0
t_TTP6
t_TTP5
t_TTP4
t_TTP3
t_TTP2
Δt_TTP
Transmitter Pulse Position for bit 1
Transmitter Pulse Position for bit 0
Transmitter Pulse Position for bit 6
Transmitter Pulse Position for bit 5
Transmitter Pulse Position for bit 4
Transmitter Pulse Position for bit 3
Transmitter Pulse Position for bit 2
Offset Transmitter Pulse Position (bit
6— bit 0)
5 – 50 MHz
50 MHz
t_DD
t_TPDD
Delay-Latency
Power Down Delay
Active to OFF
50 MHz
t_TXZR
Enable Delay
OFF to Active
50 MHz
Min
0.66
2.86
5.05
7.25
9.45
11.65
13.85
Typ
Max
1.10
3.30
5.50
7.70
9.90
12.10
14.30
1.54
3.74
5.93
8.13
10.33
12.53
14.73
0.3
0.3
900
75
1
2
3
4
5
6
7
<+0.1
0.6
0.6
2100
125
142*T
7
143*T
12
40
55
(1) t_DCCJ is the maximum amount of jitter between adjacent clock cycles.
(2) UI – Unit Interval is equivalent to one serialized data bit width (1UI = 1 / 28*PCLK). The UI scales with PCLK frequency.
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ps
ps
UI ⁽²⁾
UI
UI
UI
UI
UI
UI
UI
ns
ns
ns
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