DS92LV0411_14 Datasheet, PDF (41/53 Pages) Texas Instruments – 5 - 50 MHz Channel Link II Serializer/Deserializer with LVDS Parallel Interface

DS92LV0411, DS92LV0412
www.ti.com
SNLS331B – MAY 2010 – REVISED APRIL 2013
DS92LV0412 TYPICAL APPLICATION CONNECTION
Figure 34 shows a typical application of the DS92LV0412 for a 50 MHz 24-bit Color Display Application. The
CML inputs require 0.1 μF AC coupling capacitors to the line. The line driver includes internal termination.
Bypass capacitors are placed near the power supply pins. At a minimum, four 0.1 µF capacitors and a 4.7 µF
capacitor should be used for local device bypassing. System GPO (General Purpose Output) signals control the
PDB and BISTEN pins. The application assumes the companion deserializer (DS92LV0412) therefore the
configuration pins are also both tied Low. The interface to the host is with 1.8 V LVCMOS levels, thus the VDDIO
pin is connected also to the 1.8V rail. The Optional Serial Bus Control is not used in this example, thus the SCL,
SDA and ID[x] pins are left open. A delay cap is placed on the PDB signal to delay the enabling of the device
until power is stable. Bypass capacitors are placed near the power supply pins. Ferrite beads are placed on the
power lines for effective noise suppression.
1.8V
C11
C8
FB1
C3
FB2
C4
FB3
C5
DS92LV0412
VDDL
VDDTX
VDDL
VDDA
VDDA
VDDIO
VDDP
VDDSC
3.3V
FB4
C6
C9
C12
FB5
VDDIO
C7
C10
C13
VDDSC
TxCLKOUT+
Serial
Channel Link II
Interface
TxCLKOUT-
C1
TxOUT3+
RIN+
TxOUT3-
TxOUT2+
RIN-
C2
CMF
C15
TxOUT2-
TxOUT1+
TxOUT1-
TxOUT0+
Host
Control
BISTEN
PDB
R
C14
TxOUT0-
LOCK
PASS
1.8V
10k
RID
C1 - C2 = 0.1 PF (50 WV)
C3 ± C10, C15 = 0.1 PF
C11 - C13 = 4.7 PF
C14 = >10 PF
R = 10 k:
RID (See ID[x] Resistor Value Table)
FB1 - FB5: Impedance = 1 k:
Low DC resistance ( <1:)
ID[X]
SCL
SDA
RES
8 _GND
DAP (GND)
OEN
OSS_SEL
LFMODE
VODSEL
MAPSEL
CONFIG1
CONFIG0
SSC[2]
SSC[1]
SSC[0]
Figure 34. DS92LV0412 Typical Connection Diagram
Channel
Link
Interface
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