DS92LV0411_14 Datasheet, PDF (34/53 Pages) Texas Instruments – 5 - 50 MHz Channel Link II Serializer/Deserializer with LVDS Parallel Interface

DS92LV0411, DS92LV0412
SNLS331B – MAY 2010 – REVISED APRIL 2013
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BER Calculations
It is possible to calculate the approximate Bit Error Rate (BER). The following is required:
• Pixel Clock Frequency (MHz)
• BIST Duration (seconds)
• BIST test Result (PASS)
The BER is less than or equal to one over the product of 24 times the RxCLKIN rate times the test duration. If we
assume a 65MHz RxCLKIN, a 10 minute (600 second) test, and a PASS, the BERT is ≤ 1.07 X 10E-12
The BIST mode runs a check on the data payload bits. The LOCK pin also provides a link status. It the recovery
of the C0 and C1 bits does not reconstruct the expected clock signal, the LOCK pin will switch Low. The
combination of the LOCK and At-Speed BIST PASS pin provides a powerful tool for system evaluation and
performance monitoring.
BISTEN
(DS90UR907Q)
BISTEN
(Deserializer)
TxCLKOUT
(Diff.)
TxOUT[3:0]
(Diff.)
DATA
(internal)
PASS
Prior Result
DATA
(internal)
PASS
Prior Result
Normal
PRBS
X = bit error(s)
X
X
X
BIST Test
BIST Duration
Figure 28. BIST Waveforms
PASS
FAIL
BIST
Result
Held
Normal
34
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