DS92LV0411_14 Datasheet, PDF (29/53 Pages) Texas Instruments – 5 - 50 MHz Channel Link II Serializer/Deserializer with LVDS Parallel Interface

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DS92LV0411, DS92LV0412
SNLS331B – MAY 2010 – REVISED APRIL 2013
0.00
-2.00
VDD = 1.8V,
T_A = 25^oC
-4.00
-6.00
-8.00
-10.00
-12.00
-14.00
1.0E+02 1.0E+03 1.0E+04 1.0E+05 1.0E+06
R VALUE - LOG SCALE (:)
Figure 25. De-Emph vs. R value
POWER SAVING FEATURES
Ser — Power Down Feature (PDB)
The DS92LV0411 has a PDB input pin to ENABLE or POWER DOWN the device. This pin is controlled by the
host and is used to save power, disabling the link when the display is not needed. In the POWER DOWN mode,
the high-speed driver outputs are both pulled to VDD and present a 0V VOD state. Note – in POWER DOWN,
the optional Serial Bus Control Registers are RESET.
Ser — Stop Clock Feature
The DS92LV0411 will enter a low power SLEEP state when the RxCLKIN is stopped. A STOP condition is
detected when the input clock frequency is less than 3 MHz. The clock should be held at a static Low or high
state. When the RxCLKIN starts again, the device will then lock to the valid input RxCLKIN and then transmits
the RGB data to the desializer. Note – in STOP CLOCK SLEEP, the optional Serial Bus Control Registers values
are RETAINED.
1.8V or 3.3V VDDIO Operation
The DS92LV0411 parallel control pin bus can operate with 1.8 V or 3.3 V levels (V_DDIO) for host compatibility.
The 1.8 V levels will offer a system power savings.
OPTIONAL SERIAL BUS CONTROL
Please see the following section on the Optional Serial Bus Control Interface.
OPTIONAL BIST MODE
Please see the following section on the chipset BIST Mode for details.
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