DS92LV0411_14 Datasheet, PDF(33/53 Page) Texas Instruments – 5 - 50 MHz Channel Link II Serializer/Deserializer with LVDS Parallel Interface

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DS92LV0411_14 Datasheet, PDF (33/53 Pages) Texas Instruments – 5 - 50 MHz Channel Link II Serializer/Deserializer with LVDS Parallel Interface

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DS92LV0411, DS92LV0412

www.ti.com

SNLS331B â MAY 2010 â REVISED APRIL 2013

Built In Self Test (BIST)

An optional At-Speed Built In Self Test (BIST) feature supports the testing of the high-speed serial link. This is

useful in the prototype stage, equipment production, in-system test and also for system diagnostics. In the BIST

mode only a input clock is required along with control to the Ser and Des BISTEN input pins. The Ser outputs a

test pattern (PRBS7) and drives the link at speed. The Des detects the PRBS7 pattern and monitors it for errors.

A PASS output pin toggles to flag any payloads that are received with 1 to 24 errors. Upon completion of the

test, the result of the test is held on the PASS output until reset (new BIST test or Power Down). A high on PASS

indicates NO ERRORS were detected. A Low on PASS indicates one or more errors were detected. The duration

of the test is controlled by the pulse width applied to the Des BISTEN pin.

Inter-operability is supported between this Channel Link II device and all reverse compatible devicesâ see

respective datasheets for details on entering BIST mode and control.

Sample BIST Sequence

See Figure 27 for the BIST mode flow diagram.

Step 1: Place the serializer in BIST Mode by setting Ser BISTEN = H. The BIST Mode is enabled via the

BISTEN pin. An RxCLKIN is required for all the Ser options. When the deserializer detects the BIST mode

pattern and command the parallel data and control signal outputs are shut off.

Step 2: Place the deserializer in BIST mode by setting the BISTEN = H. The Des is now in the BIST mode and

checks the incoming serial payloads for errors. If an error in the payload (1 to 24) is detected, the PASS pin will

switch low for one half of the clock period. During the BIST test, the PASS output can be monitored and counted

to determine the payload error rate.

Step 3: To Stop the BIST mode, the deserializer BISTEN pin is set Low. The deserializer stops checking the

data and the final test result is held on the PASS pin. If the test ran error free, the PASS output will be High. If

there was one or more errors detected, the PASS output will be Low. The PASS output state is held until a new

BIST is run, the device is RESET, or Powered Down. The BIST duration is user controlled by the duration of the

BISTEN signal.

Step 4: To return the link to normal operation, the ser and des BISTEN input are set Low. The Link returns to

normal operation.

Figure 28 shows the waveform diagram of a typical BIST test for two cases. Case 1 is error free, and Case 2

shows one with multiple errors. In most cases it is difficult to generate errors due to the robustness of the link

(differential data transmission etc.), thus they may be introduced by greatly extending the cable length, faulting

the interconnect, reducing signal condition enhancements (De-Emphasis, VODSEL, or deserializer Equalization).

Normal

Step 1: SER in BIST

BIST

Wait

Step 2: Wait, DES in BIST

BIST

Start

Step 3: DES in Normal

Mode - check PASS

BIST

Stop

Step 4: SER in Normal

Figure 27. BIST Mode Flow Diagram

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