DS92LV0411_14 Datasheet, PDF (40/53 Pages) Texas Instruments – 5 - 50 MHz Channel Link II Serializer/Deserializer with LVDS Parallel Interface

DS92LV0411, DS92LV0412
SNLS331B – MAY 2010 – REVISED APRIL 2013
APPLICATIONS INFORMATION
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DISPLAY APPLICATION
The DS92LV0411 and DS92LV0412 chipset is intended for interface between a host (graphics processor) and a
Display. It supports an 24-bit color depth (RGB888) and up to 1024 X 768 display formats. In a RGB888
application, 24 color bits (R[7:0], G[7:0], B[7:0]), Pixel Clock (PCLK) and three control bits (VS, HS and DE) are
supported across the serial link with PCLK rates from 5 to 50 MHz. The chipset may also be used in 18-bit color
applications. In this application three to six general purpose signals may also be sent from host to display.
DS92LV0411 TYPICAL APPLICATION CONNECTION
Figure 33 shows a typical application of the DS92LV0411 for a 50 MHz 24-bit Color Display Application. The
LVDS inputs require external 100 ohm differential termination resistors. The CML outputs require 0.1 μF AC
coupling capacitors to the line. The line driver includes internal termination. Bypass capacitors are placed near
the power supply pins. At a minimum, four 0.1 µF capacitors and a 4.7 µF capacitor should be used for local
device bypassing. System GPO (General Purpose Output) signals control the PDB and BISTEN pins. The
application assumes the companion deserializer (DS92LV0412) therefore the configuration pins are also both
tied Low. In this example the cable is long, therefore the VODSEL pin is tied High and a De-Emphasis value is
selected by the resistor R1. The interface to the host is with 1.8 V LVCMOS levels, thus the VDDIO pin is
connected also to the 1.8V rail. The Optional Serial Bus Control is not used in this example, thus the SCL, SDA
and ID[x] pins are left open. A delay cap is placed on the PDB signal to delay the enabling of the device until
power is stable. Bypass capacitors are placed near the power supply pins. Ferrite beads are placed on the power
lines for effective noise suppression.
VDDIO
C10 C8
FB1
C3
DS92LV0411
VDDIO
VDDTX
VDDHS
C4
FB2
1.8V
C9 C11
Channel Link
Interface
LVDS
100: Terminations
Host
Control
1.8V
10k
RID
RxCLKIN-
RxCLKIN+
RxIN3-
RxIN3+
RxIN2-
RxIN2+
RxIN1-
RxIN1+
RxIN0-
RxIN0+
ID[X]
SCL
SDA
BISTEN
PDB
R
C13
CONFIG1
CONFIG0
MAPSEL
VDDP
C12 C5
VDDL
C6
VDDRX
C7
DOUT+
DOUT-
FB3
FB4
FB5
C1
Serial
Channel Link II
Interface
C2
VODSEL
De-Emph
VDDIO
R1
RES7
RES6
RES5
RES4
RES3
RES2
RES1
RES0
DAP (GND)
NOTE:
C1-C2 = 0.1 PF (50 WV)
C3-C9 = 0.1 PF
C10-C12 = 4.7 PF
C13 = >10 PF
R = 10 k:
R1 (cable insertion loss specific)
RID (see ID[x] Resistor Value Table)
FB1-FB5: Impedance = 1 k:,
low DC resistance (<1:)
Figure 33. DS92LV0411 Typical Connection Diagram
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