DS92LV0411_14 Datasheet, PDF (30/53 Pages) Texas Instruments – 5 - 50 MHz Channel Link II Serializer/Deserializer with LVDS Parallel Interface

DS92LV0411, DS92LV0412
SNLS331B – MAY 2010 – REVISED APRIL 2013
www.ti.com
Deserializer Functional Description
The Des converts a single input serial data stream to a wide parallel output bus, and also provides a signal
check for the chipset Built In Self Test (BIST) mode. The device can be configured via external pins and strap
pins or through the optional serial control bus. The Des features enhance signal quality on the link with an
integrated equalizer on the serial input and Channel Link II data encoding which provides randomization,
scrambling, and DC balanacing of the data. The Des includes multiple features to reduce EMI associated with
data transmission. This includes the randomization and scrambling of the data, the output spread spectrum clock
generation (SSCG) support. The Des features power saving features with a power down mode, and optional
LVCMOS (1.8 V) interface compatibility.
OSCILLATOR OUTPUT — OPTIONAL
The DS92LV0412 provides an optional TxCLKOUT when the input clock (serial stream) has been lost. This is
based on an internal oscillator. The frequency of the oscillator may be selected. This feature may be controlled
by the external pin or through the registers.
Clock-DATA RECOVERY STATUS FLAG (LOCK), OUTPUT ENABLE (OEN) and OUTPUT STATE SELECT
(OSS_SEL)
When PDB is driven HIGH, the CDR PLL begins locking to the serial input, LOCK is LOW and the Channel Link
interface state is determined by the state of the OSS_SEL pin.
After the DS92LV0412 completes its lock sequence to the input serial data, the LOCK output is driven HIGH,
indicating valid data and clock recovered from the serial input is available on the Channel Link outputs. The
TxCLKOUT output is held at its current state at the change from OSC_CLK (if this is enabled via OSC_SEL) to
the recovered clock (or vice versa). Note that the Channel Link outputs may be held in an inactive state (Tri-
State®) through the use of the Output Enable pin (OEN).
If there is a loss of clock from the input serial stream, LOCK is driven LOW and the state of the outputs are
based on the OSS_SEL setting (configuration pin or register).
INPUTS
PDB
L
L
H
H
H
H
OEN
X
X
L
H
L
H
Table 6. Des Output State Table
OSS_SEL
X
L
H
H
X
X
OUTPUTS
LOCK
X
L
L
L
H
H
OTHER OUTPUTS
TxCLKOUT is Tri-State
TxOUT[3:0] are Tri-State
PASS is Tri-State
TxCLKOUT is Tri-State
TxOUT[3:0] are Tri-State
PASS is HIGH
TxCLKOUT is Tri-State
TxOUT[3:0] are Tri-State
PASS is Tri-State
TxCLKOUT is Tri-State or OSC Output through Register bit
TxOUT[3:0] are Tri-State
PASS is Tri-State
TxCLKOUT is Tri-State
TxOUT[3:0] are Tri-State
PASS is HIGH
TxCLKOUT is Active
TxOUT[3:0] are Active
PASS is Active
(Normal operating mode)
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