DS92LV0411_14 Datasheet, PDF (6/53 Pages) Texas Instruments – 5 - 50 MHz Channel Link II Serializer/Deserializer with LVDS Parallel Interface

DS92LV0411, DS92LV0412
SNLS331B – MAY 2010 – REVISED APRIL 2013
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Table 1. DS92LV0411 PIN DESCRIPTIONS (continued)
Pin Name
Pin #
Power and Ground⁽¹⁾
VDDL
5
VDDP
11
VDDHS
14
VDDTX
17
VDDRX
24
VDDIO
22
GND
DAP
I/O, Type Description
Power
Power
Power
Power
Power
Power
Ground
Logic Power, 1.8 V ±5%
PLL Power, 1.8 V ±5%
TX High Speed Logic Power, 1.8 V ±5%
Output Driver Power, 1.8 V ±5%
RX Power, 1.8 V ±5%
LVCMOS I/O Power and Channel Link I/O Power 1.8 V ±5% OR 3.3 V ±10%
DAP is the large metal contact at the bottom side, located at the center of the WQFN
package. Connect to the ground plane (GND) with at least 9 vias.
(1) 1= HIGH, 0 = LOW. The VDD (V_DDn and V_DDIO) supply ramp should be faster than 1.5 ms with a monotonic rise. If slower then 1.5 ms
then a capacitor on the PDB pin is needed to ensure PDB arrives after all the VDD have settled to the recommended operating voltage.
DS92LV0412 Pin Diagram
RES 37
VDDA 38
GND 39
RIN+ 40
RIN- 41
CMF 42
VDDA 43
GND 44
GND 45
VDDSC 46
VDDSC 47
GND 48
DAP = GND
DS92LV0412
(Top View)
24 TxOUT0-
23 TxOUT0+
22 TxOUT1-
21 TxOUT1+
20 TxOUT2-
19 TxOUT2+
18 TxCLKOUT-
17 TxCLKOUT+
16 TxOUT3-
15 TxOUT3+
14 GND
13 VDDTX
Figure 2. DS92LV0412 — Top View
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