DS92LV0411_14 Datasheet, PDF (24/53 Pages) Texas Instruments – 5 - 50 MHz Channel Link II Serializer/Deserializer with LVDS Parallel Interface

DS92LV0411, DS92LV0412
SNLS331B – MAY 2010 – REVISED APRIL 2013
www.ti.com
FUNCTIONAL DESCRIPTION
The DS92LV0411 / DS92LV0412 chipset transmits and receives 24-bits of data and 3 control signals, formatted
as Channel Link LVDS data, over a single serial CML pair operating at 140 Mbps to 1.4 Gbps serial line rate.
The serial stream contains an embedded clock, video control signals and is DC-balance to enhance signal
quality and supports AC coupling.
The Des can attain lock to a data stream without the use of a separate reference clock source, which simplifies
system complexity and overall cost. The Des also synchronizes to the Ser regardless of the data pattern,
delivering true automatic “plug and lock” performance. It can lock to the incoming serial stream without the need
of special training patterns or sync characters. The Des recovers the clock and data by extracting the embedded
clock information, validating and then deserializing the incoming data stream providing a parallel Channel Link
LVDS bus to the display, ASIC, or FPGA.
The DS92LV0411 / DS92LV0412 chipset can operate with up to 24 bits of raw data with three slower speed
control bits encoded within the serial data stream. For applications that require less the maximum 24 pclk speed
bit spaces, the user will need to ensure that all unused bit spaces or parallel LVDS channels are set to valid logic
states, as all parallel lanes and 27 bit spaces will always be sampled.
Block Diagrams for the chipset are shown at the beginning of this datasheet.
PARALLEL LVDS DATA TRANSFER
The DS92LV0411/DS92LV0412 can be configured to accept/transmit 24-bit data with 2 different mapping
schemes: The normal Channel Link LVDS format (MSBs on LVDS channel 3) can be selected by configuring the
MAPSEL pin to HIGH. See Figure 15 for the normal Channel Link LVDS mapping. An alternate mapping scheme
is available (LSBs on LVDS channel 3) by configuring the MAPSEL pin to LOW. See Figure 16 for the alternate
LVDS mapping. The mapping schemes can also be selected by register control.
The alternate mapping scheme is useful in some applications where the receiving system, typically a display,
requires that the LSBs for the 24-bit color data be sent on LVDS channel 3.
SERIAL DATA TRANSFER
The DS92LV0411 transmits a 24–bit word of data in the following format: C1 and C0 represent the embedded
clock in the serial stream. C1 is always HIGH and C0 is always LOW. b[23:0] contain the scrambled RGB data,
plus two additional bits for encoding overhead. The control signals (VS,HS,DE) are also encoded within these
two additional bits. This coding scheme is generated by the DS92LV0411 and decoded by the paring
deserializer, such as the DS92LV0412, automatically.
The DS92LV0412 receives a 24 bit word of data in the format as described above. It also synchronizes to the
serializer regardless of the data pattern, delivering true automatic “plug and lock” performance. it can lock to the
incoming serial stream without the need for special training patterns or sync characters. The DS92LV0412
recovers the clock and data by extracting the embedded clock information, validating and then deserializing the
incoming data stream.
Figure 21 illustrates the serial stream per PCLK cycle.
C
1
C
0
Figure 21. Channel Link II Serial Stream
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