DS92LV0411_14 Datasheet, PDF (27/53 Pages) Texas Instruments – 5 - 50 MHz Channel Link II Serializer/Deserializer with LVDS Parallel Interface

DS92LV0411, DS92LV0412
www.ti.com
SNLS331B – MAY 2010 – REVISED APRIL 2013
VIDEO CONTROL SIGNAL FILTER
The three control bits can be used to communicate any low speed signal. The most common use for these bits is
in the display or machine vision applications. In a display application these bits are typically assigned as: Bit 26 –
DE, Bit 24 – HS, Bit 25 – VS. In the machine vision standard, Camera Link, these bits are typically assigned: Bit
26 – DVAL, Bit 24 – LVAL, Bit 25 – FVAL.
When operating the devices in Normal Mode, the Video Control Signals (DE, HS, VS) have the following
restrictions:
• Normal Mode with Control Signal Filter Enabled:
– DE and HS — Only 2 transitions per 130 clock cycles are transmitted, the transition pulse must be 3
PCLK or longer.
• Normal Mode with Control Signal Filter Disabled:
– DE and HS — Only 2 transitions per 130 clock cycles are transmitted, no restriction on minimum transition
pulse.
• VS — Only 1 transition per 130 clock cycles are transmitted, minimum pulse width is 130 clock cycles.
Video Control Signals are defined as low frequency signals with limited transitions. Glitches of a control signal
can cause a visual display error. This feature allows for the chipset to validate and filter out any high frequency
noise on the control signals. See Figure 24.
PCLK
IN
HS/VS/DE
IN
PCLK
OUT
Latency
HS/VS/DE
OUT
Pulses 1 or 2
PCLKs wide
Filetered OUT
Figure 24. Video Control Signal Filter Wavefrom
SERIALIZER FUNCTIONAL DESCRIPTION
The Ser converts a Channel Link LVDS clock and data bus (4 LVDS data channels + 1 LVDS clock) to a single
serial output data stream, and also acts as a signal generator for the chipset Built In Self Test (BIST) mode. The
device can be configured via external pins or through the optional serial control bus. The Ser features enhanced
signal quality on the link by supporting: a selectable VOD level, a selectable de-emphasis signal conditioning and
also the Channel Link II data coding that provides randomization, scrambling, and DC Balanacing of the data.
The Ser includes multiple features to reduce EMI associated with display data transmission. This includes the
randomization and scrambling of the serial data and also the system spread spectrum clock support. The Ser
features power saving features with a sleep mode, auto stop clock feature, and optional 1.8 V or 3.3V I/O
compatibility.
See also the Functional Description of the chipset's serial control bus and BIST modes.
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