DS90C124_13 Datasheet, PDF (8/31 Pages) Texas Instruments – 5-MHz to 35-MHz DC-Balanced 24-Bit FPD-Link II Serializer and Deserializer

DS90C124, DS90C241
SNLS209L – NOVEMBER 2005 – REVISED APRIL 2013
Device Pin Name
Signal Pattern
RCLK
ODD ROUT
EVEN ROUT
Figure 2. Deserializer Output Checkerboard Pattern
DOUT+
DOUT-
10 pF
100:
Differential
80%
Signal _20%
10 pF
Vdiff = (DOUT+) - (DOUT-)
t_LLHT
80%
Vdiff = 0V
20%
t_LHLT
Figure 3. Serializer LVDS Output Load and Transition Times
TCLK
80%
20%
80%
V_DD
20%
0V
t_CLKT
t_CLKT
Figure 4. Serializer Input Clock Transition Times
t_TCP
TCLK
V_DD/2
V_DD/2
V_DD/2
t_DIS
t_DIH
DIN [0:23] _VDD/2
Setup
Hold
V_DD/2
V_DD
0V
Figure 5. Serializer Setup/Hold Times
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