DS90C124_13 Datasheet, PDF (19/31 Pages) Texas Instruments – 5-MHz to 35-MHz DC-Balanced 24-Bit FPD-Link II Serializer and Deserializer

DS90C124, DS90C241
www.ti.com
SNLS209L – NOVEMBER 2005 – REVISED APRIL 2013
Receiver Termination Option 1
A single 100 Ohm termination resistor is placed across the RIN± pins (see Figure 20). This provides the signal
termination at the Receiver inputs. Other options may be used to increase noise tolerance.
Receiver Termination Option 2
For additional EMI tolerance, two 50 Ohm resistors may be used in place of the single 100 Ohm resistor. A small
capacitor is tied from the center point of the 50 Ohm resistors to ground (see Figure 23). This provides a high-
frequency low impedance path for noise suppression. Value is not critical, 4.7nF maybe used with general
applications.
Receiver Termination Option 3
For high noise environments an additional voltage divider network may be connected to the center point. This
has the advantage of a providing a DC low-impedance path for noise suppression. Use resistor values in the
range of 75Ω-2KΩ for the pullup and pulldown. Ratio the resistor values to bias the center point at 1.2V. For
example (see Figure 24): VDD=3.3V, Rpullup=1.3KΩ, Rpulldown=750Ω; or Rpullup=130Ω, Rpulldown=75Ω
(strongest). The smaller values will consume more bias current, but will provide enhanced noise suppression.
PROGRESSIVE TURN–ON (PTO)
Deserializer ROUT[23:0] outputs are grouped into three groups of eight, with each group switching about 0.5UI
apart in phase to reduce EMI, simultaneous switching noise, and system ground bounce.
APPLICATIONS INFORMATION
USING THE DS90C241 AND DS90C124
The DS90C241/DS90C124 Serializer/Deserializer (SERDES) pair sends 24 bits of parallel LVCMOS data over a
serial LVDS link up to 840 Mbps. Serialization of the input data is accomplished using an on-board PLL at the
Serializer which embeds clock with the data. The Deserializer extracts the clock/control information from the
incoming data stream and deserializes the data. The Deserializer monitors the incoming clockl information to
determine lock status and will indicate lock by asserting the LOCK output high.
DISPLAY APPLICATION
The DS90C241/DS90C124 chipset is intended for interface between a host (graphics processor) and a Display.
It supports an 18-bit color depth (RGB666) and up to 800 X 480 display formats. In a RGB666 configuration 18
color bits (R[5:0], G[5:0], B[5:0]), Pixel Clock (PCLK) and three control bits (VS, HS and DE) along with three
spare bits are supported across the serial link with PCLK rates from 5 to 35 MHz.
TYPICAL APPLICATION CONNECTION
Figure 21 shows a typical application of the DS90C241 Serializer (SER). The LVDS outputs utilize a 100 ohm
termination and 100nF coupling capacitors to the line. Bypass capacitors are placed near the power supply pins.
A system GPO (General Purpose Output) controls the TPWDNB pin. In this application the TRFB pin is tied High
to latch data on the rising edge of the TCLK. The DEN signal is not used and is tied High also. In this application
the link is short, therefore the VODSEL pin is tied Low for the standard LVDS swing. The pre-emphasis input
utilizes a resistor to ground to set the amount of pre-emphasis desired by the application.
Figure 22 shows a typical application of the DS90C124 Deserializer (DES). The LVDS inputs utilize a 100 ohm
termination and 100nF coupling capacitors to the line. Bypass capacitors are placed near the power supply pins.
A system GPO (General Purpose Output) controls the RPWDNB pin. In this application the RRFB pin is tied High
to strobe the data on the rising edge of the RCLK. The REN signal is not used and is tied High also.
POWER CONSIDERATIONS
An all CMOS design of the Serializer and Deserializer makes them inherently low power devices. Additionally,
the constant current source nature of the LVDS outputs minimize the slope of the speed vs. I_CC curve of CMOS
designs.
Copyright © 2005–2013, Texas Instruments Incorporated
Product Folder Links: DS90C124 DS90C241
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