DS90C124_13 Datasheet, PDF (15/31 Pages) Texas Instruments – 5-MHz to 35-MHz DC-Balanced 24-Bit FPD-Link II Serializer and Deserializer

DS90C124, DS90C241
www.ti.com
Pin # Pin Name
I/O
2
RESRVD
LVCMOS_I
LVDS SERIAL INTERFACE PINS
41
RIN+
LVDS_I
42
RIN−
LVDS_I
POWER / GROUND PINS
39
VDDIR
VDD
40
VSSIR
GND
47
VDDPR0
VDD
46
VSSPR0
GND
45
VDDPR1
VDD
44
VSSPR1
GND
37
VDDR1
VDD
38
VSSR1
GND
36
VDDR0
VDD
35
VSSR0
GND
30
VDDOR1
VDD
29
VSSOR1
GND
20
VDDOR2
VDD
19
VSSOR2
GND
7
VDDOR3
VDD
8
VSSOR3
GND
SNLS209L – NOVEMBER 2005 – REVISED APRIL 2013
Description
Reserved. This pin MUST be tied LOW.
Receiver LVDS True (+) Input
This input is intended to be terminated with a 100Ω load to the R_IN+ pin. The interconnect should
be AC Coupled to this pin with a 100 nF capacitor.
Receiver LVDS Inverted (−) Input
This input is intended to be terminated with a 100Ω load to the R_IN-pin. The interconnect should
be AC Coupled to this pin with a 100 nF capacitor.
Analog LVDS Voltage supply, Power
Analog LVDS Ground
Analog Voltage supply, PLL Power
Analog Ground, PLL Ground
Analog Voltage supply, PLL VCO Power
Analog Ground, PLL VCO Ground
Digital Voltage supply, Logic Power
Digital Ground, Logic Ground
Digital Voltage supply, Logic Power
Digital Ground, Logic Ground
Digital Voltage supply, LVCMOS Output Power
Digital Ground, LVCMOS Output Ground
Digital Voltage supply, LVCMOS Output Power
Digital Ground, LVCMOS Output Ground
Digital Voltage supply, LVCMOS Output Power
Digital Ground, LVCMOS Output Ground
Copyright © 2005–2013, Texas Instruments Incorporated
Product Folder Links: DS90C124 DS90C241
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