DS90C124_13 Datasheet, PDF (10/31 Pages) Texas Instruments – 5-MHz to 35-MHz DC-Balanced 24-Bit FPD-Link II Serializer and Deserializer

DS90C124, DS90C241
SNLS209L – NOVEMBER 2005 – REVISED APRIL 2013
DIN
SYMBOL N
SYMBOL N+1
SYMBOL N+2
SYMBOL N+3
t_SD
TCLK
DOUT0-23
DCA, DCB
STOP START
STOP START
STOP START
STOP START
STOP
SYMBOL N-4 BIT BIT SYMBOL N-3 BIT BIT SYMBOL N-2 BIT BIT SYMBOL N-1 BIT BIT SYMBOL N BIT
012
23
012
23
012
23
012
23
012
23
Figure 8. Serializer Delay
Ideal Data Bit
Beginning
Ideal Data Bit
End
TxOUT_E_O
t_BIT(1/2UI)
t_BIT(1/2UI)
Ideal Center Position (t_BIT/2)
t_BIT (1UI)
Figure 9. Transmitter Output Eye Opening (TxOUT_E_O)
www.ti.com
24
DIN
DOUT+
R_L
DOUT-
TCLK
VOD = (D_OUT+) – (D_{OUT -})
Differential output signal is shown as (D_OUT+) – (D_{OUT -}), device in Data Transfer mode.
Figure 10. Serializer VOD Diagram
Deserializer
8 pF
lumped
Single-ended
Signal
80%
20%
80%
20%
t_CLH
t_CHL
Figure 11. Deserializer LVCMOS/LVTTL Output Load and Transition Times
10
Submit Documentation Feedback
Copyright © 2005–2013, Texas Instruments Incorporated
Product Folder Links: DS90C124 DS90C241