DS90C124_13 Datasheet, PDF (16/31 Pages) Texas Instruments – 5-MHz to 35-MHz DC-Balanced 24-Bit FPD-Link II Serializer and Deserializer

DS90C124, DS90C241
SNLS209L – NOVEMBER 2005 – REVISED APRIL 2013
DS90C124 Pin Diagram
Deserializer - DS90C124
www.ti.com
V_DDR1
37
V_SSR1
38
V_DDIR
39
V_SSIR
40
RIN+
41
RIN-
42
RRFB
43
V_SSPR1
44
V_DDPR1
45
V_SSPR0
46
V_DDPR0
47
REN
48
PTO GROUP 1
DS90C124
48 PIN TQFP
PTO GROUP 3
24
ROUT[8]
23
ROUT[9]
22
ROUT[10]
21
ROUT[11]
20
V_DDOR2
19
V_SSOR2
18
RCLK
17
LOCK
16
ROUT[12]
15
ROUT[13]
14
ROUT[14]
13
ROUT[15]
Figure 18. TOP VIEW
FUNCTIONAL DESCRIPTION
The DS90C241 Serializer and DS90C124 Deserializer chipset is an easy-to-use transmitter and receiver pair that
sends 24-bits of parallel LVCMOS data over a single serial LVDS link from 120 Mbps to 840 Mbps throughput.
The DS90C241 transforms a 24-bit wide parallel LVCMOS data into a single high speed LVDS serial data stream
with embedded clock and scrambles / DC Balances the data to enhance signal quality to support AC coupling.
The DS90C124 receives the LVDS serial data stream and converts it back into a 24-bit wide parallel data and
recovered clock. The 24-bit Serializer/Deserializer chipset is designed to transmit data up to 10 meters over
shielded twisted pair (STP) at clock speeds from 5 MHz to 35 MHz.
The Deserializer can attain lock to a data stream without the use of a separate reference clock source; greatly
simplifying system complexity and overall cost. The Deserializer synchronizes to the Serializer regardless of data
pattern, delivering true automatic “plug and lock” performance. It will lock to the incoming serial stream without
the need of special training patterns or sync characters. The Deserializer recovers the clock and data by
extracting the embedded clock information and validating data integrity from the incoming data stream and then
deserializes the data. The Deserializer monitors the incoming clock information, determines lock status, and
asserts the LOCK output high when lock occurs. Each has a power down control to enable efficient operation in
various applications.
INITIALIZATION AND LOCKING MECHANISM
Initialization of the DS90C241 and DS90C124 must be established before each device sends or receives data.
Initialization refers to synchronizing the Serializer’s and Deserializer’s PLL’s together. After the Serializers locks
to the input clock source, the Deserializer synchronizes to the Serializers as the second and final initialization
step.
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