DS90C124_13 Datasheet, PDF (7/31 Pages) Texas Instruments – 5-MHz to 35-MHz DC-Balanced 24-Bit FPD-Link II Serializer and Deserializer

DS90C124, DS90C241
www.ti.com
SNLS209L – NOVEMBER 2005 – REVISED APRIL 2013
Deserializer Switching Characteristics
Over recommended operating supply and temperature ranges unless otherwise specified.
Symbol
t_RCP
t_RDC
t_CLH
t_CHL
Parameter
Receiver out Clock Period
RCLK Duty Cycle
LVCMOS Low-to-High
Transition Time
LVCMOS High-to-Low
Transition Time
Conditions
t_RCP = t_TCP ⁽¹⁾
C_L = 8 pF
(lumped load)
(Figure 11)⁽¹⁾
Pin/Freq.
RCLK
RCLK
ROUT [23:0],
LOCK, RCLK
Min
28.6
45
t_ROS
ROUT (7:0) Setup Data to RCLK (Figure 15)
(Group 1)
t_ROH
ROUT (7:0) Hold Data to RCLK
(Group 1)
t_ROS
ROUT (15:8) Setup Data to RCLK (Figure 15)
(Group 2)
t_ROH
ROUT (15:8) Hold Data to RCLK
(Group 2)
t_ROS
ROUT (23:16) Setup Data to
(Figure 15)
RCLK (Group 3)
t_ROH
ROUT (23:16) Hold Data to RCLK
(Group 3)
t_HZR
HIGH to TRI-STATE Delay
t_LZR
LOW to TRI-STATE Delay
t_ZHR
TRI-STATE to HIGH Delay
t_ZLR
TRI-STATE to LOW Delay
t_DD
Deserializer Delay
(Figure 13)
(Figure 12)
ROUT [7:0]
ROUT [15:8],
LOCK
ROUT [23:16]
ROUT [23:0],
RCLK, LOCK
(0.40)*
t_RCP
(0.40)*
t_RCP
(0.40)*
t_RCP
(0.40)*
t_RCP
(0.40)*
t_RCP
(0.40)*
t_RCP
RCLK
t_DRDL
Deserializer PLL Lock Time from (Figure 14) ^{(2) (1)}
Powerdown
RxIN_TOL Receiver INput TOLerance Left,
_L
RxIN_TOL Receiver INput TOLerance Right,
_R
(Figure 16)^{(3) (1) (4)}
(Figure 16)^{(3) (1) (4)}
5 MHz
35 MHz
5 MHz–35 MHz
5 MHz–35 MHz
Typ
Max
200
50
55
2.5
3.5
2.5
3.5
(29/56)*t_R
CP
(27/56)*t_R
CP
0.5*t_RCP
0.5*t_RCP
(27/56)*t_R
CP
(29/56)*t_R
CP
3
3
3
3
[4+(3/56)]
T +5.9
5
5
10
10
10
10
[4+(3/56)]
T +14
50
50
0.25
0.25
Units
ns
%
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ms
ms
UI
UI
(1) Specification is ensured by characterization and is not tested in production.
(2) The Deserializer PLL lock time (t_DRDL) may vary depending on input data patterns and the number of transitions within the pattern.
(3) RxIN_TOL is a measure of how much phase noise (jitter) the deserializer can tolerate in the incoming data stream before bit errors
occur. It is a measurement in reference with the ideal bit position, please see AN-1217 (SNLA053) for detail.
(4) UI – Unit Interval, equivalent to one ideal serialized data bit width. The UI scales with frequency.
AC TIMING DIAGRAMS AND TEST CIRCUITS
Device Pin Name
Signal Pattern
TCLK
ODD DIN
EVEN DIN
Figure 1. Serializer Input Checkerboard Pattern
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