DS90C124_13 Datasheet, PDF (11/31 Pages) Texas Instruments – 5-MHz to 35-MHz DC-Balanced 24-Bit FPD-Link II Serializer and Deserializer

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DS90C124, DS90C241
SNLS209L – NOVEMBER 2005 – REVISED APRIL 2013
RIN0-23
DCA, DCB
START
STOP START
STOP START
STOP START
STOP
BIT SYMBOL N BIT BIT SYMBOL N+1 BIT BIT SYMBOL N+2 BIT BIT SYMBOL N+3 BIT
012
23
012
23
012
23
012
23
t_DD
RCLK
ROUT0-23
SYMBOL N-3
SYMBOL N-2
SYMBOL N-1
Figure 12. Deserializer Delay
SYMBOL N
REN
500:
VREF
C_L = 8pF
+
-
VREF = V_DD/2 for t_ZLR or t_LZR,
VREF = 0V for t_ZHR or t_HZR
VOH
REN
VOL
V_DD/2
t_LZR
V_DD/2
t_ZLR
VOL
ROUT [23:0]
VOH
t_HZR
VOL + 0.5V
t_ZHR
VOL + 0.5V
VOH - 0.5V
VOH + 0.5V
Note: C_L includes instrumentation and fixture capacitance within 6 cm of ROUT[23:0]
Figure 13. Deserializer TRI-STATE Test Circuit and Timing
2.0V
PWDN
RIN±
LOCK TRI-STATE
ROUT [0:23]
t_DRDL
TRI-STATE
0.8V
}v[š Œ
TRI-STATE
t_HZR or t_LZR
TRI-STATE
RCLK
TRI-STATE
TRI-STATE
REN
Figure 14. Deserializer PLL Lock Times and RPWDNB TRI-STATE Delay
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