DS90C124_13 Datasheet, PDF (23/31 Pages) Texas Instruments – 5-MHz to 35-MHz DC-Balanced 24-Bit FPD-Link II Serializer and Deserializer

www.ti.com
3.3V
C5
C6
C7
C8
DS90C124, DS90C241
SNLS209L – NOVEMBER 2005 – REVISED APRIL 2013
DS90C124 (DES)
VDDIR
VDDPR0
VDDPR1
3.3V
C1
C2
VDDOR1
VDDOR2
VDDOR3
VDDR0
VDDR1
C3
C4
C1 to C8 = 0.1 PF to 0.01 PF
C9 = 100 nF; 50 WVDC, NPO or X7R
C10 = 100 nF; 50 WVDC, NPO or X7R
R1 = 100:
C9
Serial
LVDS
Interface
R1
C10
GPO
3.3V
RPWDNB = System GPO
REN = High (ON)
RRFB = High (Rising edge)
RESRVD = Low
RIN+
RIN-
RPWDNB
REN
RRFB
RESRVD
ROUT0
ROUT1
ROUT2
ROUT3
ROUT4
ROUT5
ROUT6
ROUT7
ROUT8
ROUT9
ROUT10
ROUT11
ROUT12
ROUT13
ROUT14
ROUT15
ROUT16
ROUT17
ROUT18
ROUT19
ROUT20
ROUT21
ROUT22
ROUT23
RCLK
LOCK
LVCMOS
Parallel
Interface
Figure 22. DS90C124 Tyical Application Connection
DS90C241
0.1 PF
100:
0.1 PF
0.1 PF
50:
4.7 nF
50:
0.1 PF
RIN+
DS90C124
RIN-
Figure 23. Receiver Termination Option 2
Copyright © 2005–2013, Texas Instruments Incorporated
Product Folder Links: DS90C124 DS90C241
Submit Documentation Feedback
23