DS90C124_13 Datasheet, PDF (1/31 Pages) Texas Instruments – 5-MHz to 35-MHz DC-Balanced 24-Bit FPD-Link II Serializer and Deserializer

DS90C124, DS90C241
www.ti.com
SNLS209L – NOVEMBER 2005 – REVISED APRIL 2013
DS90C241 and DS90C124 5-MHz to 35-MHz DC-Balanced 24-Bit FPD-Link II Serializer and
Deserializer
Check for Samples: DS90C124, DS90C241
FEATURES
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•2 5-MHz to 35-MHz clock embedded and DC-
Balancing 24:1 and 1:24 data transmissions
• User defined pre-emphasis driving ability
through external resistor on LVDS outputs and
capable to drive up to 10-meter shielded
twisted-pair cable
• User-selectable clock edge for parallel data on
both transmitter and receiver
• Internal DC balancing encode and decode –
Supports AC-coupling interface with no
external coding required
• Individual power-down controls for both
transmitter and receiver
• Embedded clock CDR (clock and data
recovery) on receiver and no external source
of reference clock needed
• All codes RDL (random data lock) to support
live-pluggable applications
• LOCK output flag to ensure data integrity at
receiver side
• Balanced T_SETUP and T_HOLD between RCLK and
RDATA on receiver side
• PTO (progressive turn-on) LVCMOS outputs to
reduce EMI and minimize SSO effects
• All LVCMOS inputs and control pins have
internal pulldown
• On-chip filters for PLLs on transmitter and
receiver
• Temperature range –40°C to +105°C
• Greater than 8-kV HBM ESD tolerant
• Meets AEC-Q100 compliance
• Power supply range 3.3V ± 10%
• 48-pin TQFP package
DESCRIPTION
The DS90C241 and DS90C124 chipset translates a
24-bit parallel bus into a fully transparent data and
control LVDS serial stream with embedded clock
information. This single serial stream simplifies
transferring a 24-bit bus over PCB traces or over
cable by eliminating the skew problems between
parallel data and clock paths. It saves system cost by
narrowing data paths, which in turn reduces PCB
layers, cable width, and connector size and pins.
The DS90C241 and DS90C124 incorporate LVDS
signaling on the high-speed I/O. LVDS provides a
low-power and low-noise environment for reliably
transferring data over a serial transmission path. By
optimizing the serializer output edge rate for the
operating frequency range, EMI is further reduced.
In addition, the device features pre-emphasis to boost
signals over longer distances using lossy cables.
Internal DC balanced encoding and decoding
supports AC-coupled interconnects.
1
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2
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2005–2013, Texas Instruments Incorporated