DS90C124_13 Datasheet, PDF (13/31 Pages) Texas Instruments – 5-MHz to 35-MHz DC-Balanced 24-Bit FPD-Link II Serializer and Deserializer

DS90C124, DS90C241
www.ti.com
PIN ASSIGNMENTS
SNLS209L – NOVEMBER 2005 – REVISED APRIL 2013
DS90C241 Serializer Pin Descriptions
Pin # Pin Name
I/O
Description
LVCMOS PARALLEL INTERFACE PINS
4-1,
48-44,
41-32,
29-25
DIN[23:0]
LVCMOS_I Transmitter Parallel Interface Data Input Pins. Tie LOW if unused, do not float.
10
TCLK
LVCMOS_I Transmitter Parallel Interface Clock Input Pin. Strobe edge set by TRFB configuration pin.
CONTROL AND CONFIGURATION PINS
9
TPWDNB
LVCMOS_I Transmitter Power Down Bar
TPWDNB = H; Transmitter is Enabled and ON
TPWDNB = L; Transmitter is in power down mode (Sleep), LVDS Driver D_OUT (+/-) Outputs are in
TRI-STATE stand-by mode, PLL is shutdown to minimize power consumption.
18
DEN
LVCMOS_I
Transmitter Data Enable
DEN = H; LVDS Driver Outputs are Enabled (ON).
DEN = L; LVDS Driver Outputs are Disabled (OFF), Transmitter LVDS Driver D_OUT (+/-) Outputs
are in TRI-STATE, PLL still operational and locked to TCLK.
23
PRE
LVCMOS_I
Pre-emphasis Level Select
PRE = NC (No Connect); Pre-emphasis is Disabled (OFF).
Pre-emphasis is active when input is tied to VSS through external resistor R_PRE. Resistor value
determines pre-emphasis level. Recommended value R_PRE ≥ 3 kΩ; I_max = [(1.2/R)*20], R_min = 3
kΩ
11
TRFB
LVCMOS_I
Transmitter Clock Edge Select Pin
TRFB = H; Parallel Interface Data is strobed on the Rising Clock Edge.
TRFB = L; Parallel Interface Data is strobed on the Falling Clock Edge
12
VODSEL
LVCMOS_I
VOD Level Select
VODSEL = L; LVDS Driver Output is ≈±400 mV (R_L = 100Ω)
VODSEL = H; LVDS Driver Output is ≈±750 mV (R_L = 100Ω)
For normal applications, set this pin LOW. For long cable applications where a larger VOD is
required, set this pin HIGH.
5
DCAOFF
LVCMOS_I Reserved. This pin MUST be tied LOW.
8
DCBOFF
LVCMOS_I Reserved. This pin MUST be tied LOW.
13
RESRVD
LVCMOS_I Reserved. This pin MUST be tied LOW.
LVDS SERIAL INTERFACE PINS
20
DOUT+
LVDS_O
Transmitter LVDS True (+) Output.
This output is intended to be loaded with a 100Ω load to the D_OUT+ pin. The interconnect should
be AC Coupled to this pin with a 100 nF capacitor.
19
DOUT−
LVDS_O
Transmitter LVDS Inverted (-) Output
This output is intended to be loaded with a 100Ω load to the D_OUT-pin. The interconnect should be
AC Coupled to this pin with a 100 nF capacitor.
POWER / GROUND PINS
22
VDDDR
VDD
Analog Voltage Supply, LVDS Output Power
21
VSSDR
GND
Analog Ground, LVDS Output Ground
16
VDDPT0
VDD
Analog Voltage supply, VCO Power
17
VSSPT0
GND
Analog Ground, VCO Ground
14
VDDPT1
VDD
Analog Voltage supply, PLL Power
15
VSSPT1
GND
Analog Ground, PLL Ground
30
VDDT
VDD
Digital Voltage supply, Tx Serializer Power
31
VSST
GND
Digital Ground, Tx Serializer Ground
7
VDDL
VDD
Digital Voltage supply, Tx Logic Power
6
VSSL
GND
Digital Ground, Tx Logic Ground
42
VDDIT
VDD
Digital Voltage supply, Tx Input Power
43
VSSIT
GND
Digital Ground, Tx Input Ground
24
VSS
GND
ESD Ground
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