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| DS90C124_13 Datasheet, PDF (12/31 Pages) Texas Instruments – 5-MHz to 35-MHz DC-Balanced 24-Bit FPD-Link II Serializer and Deserializer | |||
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DS90C124, DS90C241
SNLS209L â NOVEMBER 2005 â REVISED APRIL 2013
RCLK
VDD/2
tLOW
tHIGH
VDD/2
ROUT [7:0]
tROS
(group 1)
VDD/2
Data Valid
Before RCLK
tROH
(group 1)
Data Valid
After RCLK
VDD/2
1/2 UI
tROS
(group 2)
ROUT [15:8], LOCK
VDD/2
Data Valid
Before RCLK
tROH
(group 2)
1/2 UI
Data Valid
After RCLK
VDD/2
1/2 UI
tROS
(group 3)
ROUT [23:16]
VDD/2
Data Valid
Before RCLK
tROH
(group 3)
1/2 UI
Data Valid
After RCLK
VDD/2
Figure 15. Deserializer Setup and Hold Times
Ideal Data Bit
Beginning
Sampling
Window
Ideal Data Bit
End
RxIN_TOL -L
RxIN_TOL -R
Ideal Sampling Position
( )tBIT
2
tBIT
(1UI)
RxIN_TOL_L is the ideal noise margin on the left of the figure, with respect to ideal.
RxIN_TOL_R is the ideal noise margin on the right of the figure, with respect to ideal.
Figure 16. Receiver Input Tolerance (RxIN_TOL) and Sampling Window
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Product Folder Links: DS90C124 DS90C241
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