DS90C124_13 Datasheet, PDF (14/31 Pages) Texas Instruments – 5-MHz to 35-MHz DC-Balanced 24-Bit FPD-Link II Serializer and Deserializer

DS90C124, DS90C241
SNLS209L – NOVEMBER 2005 – REVISED APRIL 2013
DS90C241 Pin Diagram
Serializer - DS90C241
www.ti.com
DIN[10]
37
DIN[11]
38
DIN[12]
39
DIN[13]
40
DIN[14]
41
V_DDIT
42
V_SSIT
43
DIN[15]
44
DIN[16]
45
DIN[17]
46
DIN[18]
47
DIN[19]
48
DS90C241
48 PIN TQFP
24
V_SS
23
PRE
22
V_DDDR
21
V_SSDR
20
DOUT+
19
DOUT-
18
DEN
17
V_SSPT0
16
V_DDPT0
15
V_SSPT1
14
V_DDPT1
13
RESRVD
Figure 17. TOP VIEW
DS90C124 Deserializer Pin Descriptions
Pin # Pin Name
I/O
Description
LVCMOS PARALLEL INTERFACE PINS
25-28, ROUT[7:0]
31-34
LVCMOS_O Receiver LVCMOS level Outputs – Group 1
13-16, ROUT[15:8]
21-24
LVCMOS_O Receiver LVCMOS level Outputs – Group 2
3-6, 9- ROUT[23:16] LVCMOS_O Receiver LVCMOS level Outputs – Group 3
12
18
RCLK
LVCMOS_O Parallel Interface Clock Output Pin. Strobe edge set by RRFB configuration pin.
CONTROL AND CONFIGURATION PINS
43
RRFB
48
REN
LVCMOS_I
LVCMOS_I
Receiver Clock Edge Select Pin
RRFB = H; R_OUT LVCMOS Outputs strobed on the Rising Clock Edge.
RRFB = L; R_OUT LVCMOS Outputs strobed on the Falling Clock Edge.
Receiver Data Enable
REN = H; R_OUT[23-0] and RCLK are Enabled (ON).
REN = L; R_OUT[23-0] and RCLK are Disabled (OFF), Receiver R_OUT[23-0] and RCLK Outputs are
in TRI-STATE, PLL still operational and locked to TCLK.
1
RPWDNB
LVCMOS_I Receiver Power Down Bar
RPWDNB = H; Receiver is Enabled and ON
RPWDNB = L; Receiver is in power down mode (Sleep), R_OUT[23-0], RCLK, and LOCK are in
TRI-STATE stand-by mode, PLL is shutdown to minimize power consumption.
17
LOCK
LVCMOS_O
LOCK indicates the status of the receiver PLL
LOCK = H; receiver PLL is locked
LOCK = L; receiver PLL is unlocked, R_OUT[23-0] and RCLK are TRI-STATED
14
Submit Documentation Feedback
Copyright © 2005–2013, Texas Instruments Incorporated
Product Folder Links: DS90C124 DS90C241