DS90C124_13 Datasheet, PDF (24/31 Pages) Texas Instruments – 5-MHz to 35-MHz DC-Balanced 24-Bit FPD-Link II Serializer and Deserializer

DS90C124, DS90C241
SNLS209L – NOVEMBER 2005 – REVISED APRIL 2013
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DS90C241
0.1 PF
100:
0.1 PF
VDD
0.1 PF
R_PU
50:
R_PD ^{4.7 nF}
50:
0.1 PF
RIN+
DS90C124
RIN-
Figure 24. Receiver Termination Option 3
Truth Tables
TPWDNB
(Pin 9)
L
H
H
H
RPWDNB
(Pin 1)
L
H
H
H
Table 1. DS90C241 Serializer Truth Table
DEN
(Pin 18)
X
L
H
H
Tx PLL Status
(Internal)
X
X
Not Locked
Locked
LVDS Outputs
(Pins 19 and 20)
Hi Z
Hi Z
Hi Z
Serialized Data with Embedded Clock
Table 2. DS90C124 Deserializer Truth Table
REN
(Pin 48)
X
L
Rx PLL Status
(Internal)
X
X
ROUTn and RCLK
(See Pin Diagram)
Hi Z
Hi Z
H
Not Locked
Hi Z
H
Locked
Data and RCLK Active
LOCK
(Pin 17)
Hi Z
L = PLL Unocked;
H = PLL Locked
L
H
24
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