DS90UB928Q-Q1 Datasheet, PDF (7/69 Pages) Texas Instruments – 5 MHz to 85 MHz 24-bit Color FPD-Link III to FPD-Link Deserializer With Bidirectional Control Channel

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DS90UB928Q-Q1
SNLS417C – MARCH 2013 – REVISED JULY 2016
7 Specifications
7.1 Absolute Maximum Ratings^{(1) (2)}
Supply Voltage – V_DD33 ⁽³⁾
Supply Voltage – V_DDIO ⁽³⁾
LVCMOS I/O Voltage
MIN
−0.3
−0.3
−0.3
MAX
4
4
(V_DDIO +
0.3)
UNIT
V
V
V
Deserializer Input Voltage
−0.3
2.75
V
Junction Temperature
150
°C
Storage temperature, T_stg
−65
150
°C
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) For soldering specifications, see product folder at www.ti.com and SNOA549.
(3) The DS90UB928Q-Q1V_DD33 and V_DDIO voltages require a specific ramp rate during power up. The power supply ramp time must be less
than 1.5 ms with a monotonic rise.
7.2 ESD Ratings
V_(ESD)
Electrostatic
discharge
Human body model (HBM), per AEC Q100-002, all pins⁽¹⁾
Charged device model (CDM), per AEC Q100-011, all pins
Machine model (MM)
(IEC, powered-up only)
R_D = 330 Ω, C_S = 150 pF
Air Discharge (Pins 40, 41, 44, and 45)
Contact Discharge (Pins 40, 41, 44, and 45)
(ISO10605)
R_D = 330 Ω, C_S = 150 pF
Air Discharge (Pins 40, 41, 44, and 45)
Contact Discharge (Pins 40, 41, 44, and 45)
(ISO10605)
R_D = 2 kΩ, C_S = 150 pF or
330 pF
Air Discharge (Pins 40, 41, 44, and 45)
Contact Discharge (Pins 40, 41, 44, and 45)
VALUE
±8000
±1250
±250
±15000
±8000
±15000
±8000
±15000
±8000
(1) AEC Q100-002 indicates HBM stressing is done in accordance with the ANSI/ESDA/JEDEC JS-001 specification.
UNIT
V
V
V
V
V
V
V
V
V
7.3 Recommended Operating Conditions
Supply Voltage (V_DD33)⁽¹⁾
LVCMOS Supply Voltage (V_DDIO)^{(1) (2)}
Operating Free Air
Temperature (T_A)
PCLK Frequency (out of TxCLKOUT±)
Supply Noise⁽³⁾
Connect V_DDIO to 3.3 V and use 3.3 V IOs
Connect V_DDIO to 1.8 V and use 1.8 V IOs
MIN NOM MAX UNIT
3 3.3 3.6 V
3 3.3 3.6 V
1.71 1.8 1.89 V
−40
25 105 °C
5
85 MHz
100 mV_P-P
(1) The DS90UB928Q-Q1V_DD33 and V_DDIO voltages require a specific ramp rate during power up. The power supply ramp time must be less
than 1.5 ms with a monotonic rise.
(2) V_DDIO should not exceed V_DD33 by more than 300 mV (V_DDIO < V_DD33 + 0.3 V).
(3) Supply noise testing was done with minimum capacitors on the PCB. A sinusoidal signal is AC-coupled to the V_DD33 and V_DDIO supplies
with amplitude >100 mVp-p measured at the device VDD33 and VDDIO pins. Bit error rate testing of input to the Ser and output of the
Des with 10 meter cable shows no error when the noise frequency on the Ser is less than 50 MHz. The Des on the other hand shows no
error when the noise frequency is less than 50 MHz.
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